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As chip dimensions decrease, I-line processes remain of interest for most uncritical layers: they provide the needed performance at a low cost and high throughput. However the critical dimensions (CD) and overlay requirements for the newest technologies are much tighter than they used to be, reducing significantly the process windows. Sources of variations of CD range and CD mean should be well known and the process window set up so as to minimize the sensitivity to small variations.For lower resist thickness, although using partially dyed I-line resist, one may have to deal with huge swing effects. Resist thickness and stack variations are then the main contributors to the high CD distribution This article focuses on CD instabilities caused by resist thickness fluctuations in the case where a stack layer is subject to variations.The influence of resist thickness variations is first considered, pointing out the importance of thickness control methods. The real resist thickness repartition on stacked wafers depends not only on global coating uniformity but also on local topography. Some examples of resist repartition and its impact on CD-uniformity are provided. The added contributions of resist and stack to a global swing effect are then discussed on the basis of experimental data. Significant differences of swing behavior are experimentally observed between critical chip structures and the usually monitored PCI kerf structure. A simulation illustrates the effect of the local stack thickness and resist thickness and to better understand those differences, together with cross section thickness measurements. The choice of an appropriate CD control structure is finally dealt with.

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