SiC power devices have reached a high market penetration, especially for high-voltage applications like switch mode power supplies. In the past, however, the superior material properties like, e.g., good thermal conductivity, have often not been put to full use due to the limitations of current packaging techniques. Especially the inferior thermal conductivity of current die attach materials have been an obstacle to realise the full potential of SiC technologies. In this paper, we describe in detail the use of diffusion solder for the die attach of SiC chips. Replacing the conventional solder layer by a thin metal stack for diffusion soldering, the thermal conductivity of the device is significantly improved. In addition, we show the positive impact of diffusion soldering on the assembly process and on the device reliability. These results are interesting for, both, SiC diodes and switches.

In this paper we compare the thermal behavior of identical SiC Schottky diodes mounted in i) a standard TO220 package (TO220) with non-isolated backside applying standard soft solder and diffusion solder die attach with ii) a so called FULLPAK TO220 package (TO220FP, only diffusion soldering). Depending on the solder technique the heat transport from the junction area of the SiC Schottky diode to the heat sink or to the package backside is improved for the diodes mounted via diffusion solder. For small chips this holds even for TO220FP in comparison to TO220 with standard solder. Simulations of the vertical temperature distribution after electrically heating with a half sine wave for 10ms up to 190W show a decrease of the maximal junction temperature of the SiC Schottky diode from TJ=260 °C to TJ=180 °C if the diffusion solder is used independent from the package type.

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With the help of an improved die attach the Rth,jc of SiC Schottky diodes can be reduced by 40-50% at a given chip size. This enables a significant higher power density for these SiC diode chips, resulting in a chip shrink of ~ 35% for a given nominal current. This has a significant impact not only on the cost position of the device but also on the switching performance of the diodes, as their capacitive charge directly scales with the chip area. Of course these advantages are accompanied by a small penalty in static losses as the Vf of the diodes at nominal current also slightly increases by the chip shrink. However, the reduction of switching losses dominates upon the marginally increased static losses besides full load operation conditions (which are pretty exceptional in today’s SiC Schottky diode applications) combined with frequencies below 130 kHz. This allows a better competitive positioning against fast Si-based diodes and improved system efficiency at the same time.

Thin AU2Cu6Sn2 solder joints have been identified to provide improved electrical and thermal device performance compared to thicker solder joints [1].Both the material high thermal conductivity and the reduced joint thickness improve the thermal dissipation through the solder joint , making the thin AU2Cu6Sn2 solder layer very attractive for high power devices. In this paper, we establish a material model for the AU2Cu6Sn2 material in order to study solder thermal fatigue using finite element analysis.