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In Time-Sensitive Networks (TSN) applications with the highest real-time flow requirements are deployed using the Time-Aware Shaper which requires careful planning and scheduling of flows before deployment. Such deployments lack support for dynamic industrial scenarios such as modular machine assembly and reconfiguration, which require a flexible transition between real-time tasks. In contrast, state-of-theart techniques rely on flow rescheduling and deployment in conjunction with undesired network downtime. Existing works on adapting schedules to traffic admissions are limited in their ability to choose suitable flows to account for future tasks.In this paper, we aim to leverage the flexibility of scheduler configurations to enable TSN dynamic reconfigurability at runtime. We propose a notion of flexibility for TSN Time-Aware Shaper schedules which we utilize to decide the admissibility of consecutive real-time tasks.

SummaryTelecommunication providers continuously evolve their network infrastructure by increasing performance, lowering time to market, providing new services, and reducing the cost of the infrastructure and its operation. Network function virtualization (NFV) on commodity hardware offers an attractive, low‐cost platform to establish innovations much faster than with purpose‐built hardware products. Unfortunately, implementing NFV on commodity processors does not match the performance requirements of the high‐throughput data plane components in large carrier access networks. Therefore, programmable hardware architectures like field programmable gate arrays (FPGAs), network processors, and switch silicon supporting the flexibility of the P4 language offer a promising way to account for both performance requirements and the demand to quickly introduce innovations into networks. In this article, we propose a way to offer residential network access with programmable packet processing architectures. On the basis of the highly flexible P4 programming language, we present a design and open source implementation of a broadband network gateway (BNG) data plane that meets the challenging demands of BNGs in carrier‐grade environments. In addition, we introduce a concept of hybrid openBNG design, realizing the required hierarchical quality of service (HQoS) functionality in a subsequent FPGA. The proposed evaluation results show the desired performance characteristics, and our proposed design together with upcoming P4 hardware can offer a giant leap towards highest performance NFV network access.

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