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As 3DIC with through silicon vias (TSV) approaches high volume manufacturing readiness the importance of precision backgrinding has become increasingly more evident. Active management of the backgrinding process has multiple benefits in that it reduces the risk of wafer backside contamination due to premature contact with vias, it enables optimization of the post-thinning residual silicon thickness and the final via reveal process. It can compensate for poor via fabrication depth uniformity and less than ideal temporary bonding total thickness variation (TTV). In this paper we will demonstrate the utility of two tools that when used together can systematically produce thin TSV containing wafers to their optimal thickness while protecting the wafers from particulate contamination. The first instrument in this process scheme is a metrology tool that utilizes IR reflectance to measure the silicon thickness remaining between the bottom of the TSV and backside surface of the wafer. These measurements are then transferred to a special grinding tool that can interpret the data and make changes to the grinding depth within the wafer so as to leave thickness of silicon above the TSVs as uniform as possible. Having removed the bulk of the Si through mechanical grinding and Chem/Mech polishing, the next step in the via-middle process is to remove the last few microns of Si overburden to expose the vias. By leaving a shallower Si layer above the TSV during the thinning process compared to current process, the final via reveal process time can be reduced. Also the need for rework in this process because of the wafer-to-wafer variability in the remaining silicon thickness above the TSV can be eliminated. In addition to measuring the pre-grinding Si thickness, the IR reflectance measurement tool can be used to verify the remaining silicon thickness post grind, establishing thinning process feedback and via reveal process feed-forward data.

The continued challenge to keep up with Moore's law with aggressive device scaling, and shrinking wiring dimensions established perpetual need for novel materials and dictates ever tighter semiconductor process fidelity. Despite large progress with reducing defect densities on the device side of Si wafers, considerably less attention is being paid to the wafer back-side. Back-side wafer defects have been shown to reduce yield by leading to die breakage during packaging processes. Scratches and voids formed on the back-side of the wafer during various manufacturing processes have been shown to create weak spots on the wafer, which can act as initiation points for die crack formation and propagation. In this paper, we present the technical details of a back-side wet etch clean process which helps reducing back-side defect densities significantly. The process is set up on a single wafer wet etch tool at IBM's East Fishkill 300 mm wafer fabrication facility. The process removes the outer back-side layer of the silicon wafer which has become defective and damaged as a result of previous processing steps. This new defect removal process increases die strength, which is measured as wafer mechanical strength, and removes surface defects from the back-side of the wafer. Our results show that removal of 15–30 microns from the wafer back-side reduces the amount of cosmetic defects on the back-side of the wafer by 90%, while increasing die strength by 60%. The effects of the back-side wet etch clean process on the wafer optical appearance and mechanical properties were characterized, and supporting data such as atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), defect inspection, thermal interface material adhesion test, and die strength is included. Results from package level modules indicate an increase in reliability compared to the uncleaned Si back-side. It can be concluded that wet Si removal process described in this paper is a viable method to reduce the back-side defect density with an associated increase in final module product yield.