No abstract

A 512 x 512 monolithic PtSi Schottky Barrier Diode (SBD) array that was designed, fabricated and tested at EG &G Reticon will be discussed. The array uses a novel line-addressed charge -accumulation (LACA) CCD in an interline configuration for the vertical registers and a multiple-readout register for high speed readout. The LACA readout structure has two distinct advantages over the conventional interline CCD structure. First, the LACA register occupies a very small area while still providing enough charge handling capacity 'for the Schottky barrier detector. As a result, the 30.tm x 30 p.m pixels have a fill factor of 54% when designed with a 2.5 µm minimum dimension CCD process. Secondly, since the register operates in a charge accumulation mode, it has an extremely high effective charge accumulation efficiency. In the horizontal register, four readout structures are used to increase the overall pixel readout rate. A 75 Hz frame rate is achieved when the horizontal clock rate is 5 MHz. A CCD bending structure is utilized at each output to eliminate any coupling from the common clock lines. Each output has an electron sensitivity of greater than 5 .tV /e. The quantum yield of the platinum silicide SBDs has been between 15 and 25 %. The chip dimensions are 748 mil x 748 mil, of which 604 mil x 604 mil is photosensitive. ABSTRACTA 512 x 512 monolithic PtSi Schottky Barrier Diode (SBD) array that was designed, fabricated and tested at EG&G Reticon will be discussed. The array uses a novel line-addressed charge-accumulation (LACA) CCD in an interline configuration for the vertical registers and a multiple-readout register for high speed readout. The LACA readout structure has two distinct advantages over the conventional interline CCD structure. First, the LACA register occupies a very small area while still providing enough charge handling capacity »for the Schottky barrier detector. As a result, the 30 |im x 30 |im pixels have a fill factor of 54% when designed with a 2.5 Jim minimum dimension CCD process. Secondly, since the register operates in a charge accumulation mode, it has an extremely high effective charge accumulation efficiency. In the horizontal register, four readout structures are used to increase the overall pixel readout rate. A 75 Hz frame rate is achieved when the horizontal clock rate is 5 MHz. A CCD bending structure is utilized at each output to eliminate any coupling from the common clock lines. Each output has an electron sensitivity of greater than 5 jiV/e. The quantum yield of the platinum silicide SBDs has been between 15 and 25%. The chip dimensions are 748 mil x 748 mil, of which 604 mil x 604 mil is photosensitive.