The implementation and validation of a common DFT architecture for a new product family of PowerPC based microprocessors for various automotive applications supporting highest quality levels and low-cost test is a big challenge. When this new architecture has to satisfy the requirements of two semiconductor companies using two different CADflows based on differentATPG tools coming with incompatible on-chip scan compression solutions, the task becomes even more complex. This paper describes the result of this major effort and shows the problems encountered along the way.

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For parallel simulation of VLSI circuits on transistor level a sophisticated partitioning of the circuits into subcircuits is crucial. Each net connecting the subcircuits causes additional communication and computation effort. As the slave processors simulating the subcircuits advance synchronously in time, the computation effort for each subcircuit should be approximately the same. In this paper a new approach for partitioning VLSI circuits on transistor level yielding a low number of interconnects between the subcircuits and balanced subcircuit sizes is presented. Simulation of industrial circuits using this partitioning is up to 41% faster than with other known partitioning approaches for parallel analog simulation.

In a VHDL-based design flow for application speciJic integrated circuits, VITAL provides a uniform methodology for developing ASIC libraries for signoff simulation. The PTT4 Standard includes specialized routines for describing behavior and timing of ASIC cells and integrates backannotation via Standard Delay Format (SDF)). One of the key issues of the VITAL initiative was to accelerate simulntion performance at gate level by allowing only a restricted set of VHDL. In this papec we present an eficient implementation of the VITAL-Standard in our objectoriented, event-driven logic simulation tool OLIVI A. First pmmising results concerning simulation performance compared to conventional VHDL-Simulators are given.