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We report device mobility >500 cm2/V•s in a scalable process suitable for electronic backplanes for large area OLED displays. Ceramic substrates as large as 4x4 inches were fabricated utilizing planarized regions of Single Crystal Silicon (SCS).

We report device mobility >300 cm 2 /V•s in a scalable process suitable for electronic backplanes for large area OLED displays. Single crystal Si spheres ~800 μm are planarized to form device substrates. Performance of transistors on spheres andCzochralski (CZ) silicon wafers are compared.

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An inductively coupled plasma (ICP) chemical vapor deposition (CVD) chamber has been modified to include a grounded, perforated, separator plate below the high density plasma source. A low-temperature (150 • C) ICP-CVD process for nanocrystalline Si (nc-Si) deposition has been developed using the modified plasma chamber. The separator plate causes an increase in hydrogen partial pressure from the species released from the deposit on itself and also minimizes the ion bombardment of the substrate placed on the grounded electrode below it. As a result, nc-Si deposition was achieved with high growth rates (>6 Ås −1 ) and without having to dilute the SiH 4 precursor gas with H 2 . The films are characterized by Raman spectroscopy, x-ray diffraction, and photo-conductivity measurements. The developed process, scalable to large areas, is advantageous for devices with large area and flexible electronics such as solar cells and thin-film transistors.