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An analytical model is developed to predict the out of plane deformation in multilayered thin stacks subjected to uniform temperature loading. CTE mismatches among the components (chip, substrate, underfill, flip-chip interconnect or C4s) are the driving force for both first and second levels interconnect reliability concerns. The 6rst level failure includes die cracking and undertill delamination whereas the second level. interconnects are concerned with the BGA fatigue and non-.wetting or partial wetting during the assembly process. In this study, a proper formula for effective moduli of the complex geometry, such as solder (C4) I underfill layer, is presented.An analytical formulation for the out of plane displacement of the chip substrate structure under temperature variation AT of as high as 205°C as expected in lead (Pb) free solder applications during reflow, is developed using the effective. moduli. The warpage resulting from the analytical formulation.is compared with the two-dimensional and three-dimensional finite element analysis (FEA). The importance and challenges. in the analytical modeling aspect of the thermo-mechanical, behavior of the flip chip or chip on board assembly is emphasized. The study helps to design more reliable components or assemblies w i t h the design parameters being optimized in the early stage of the development. KEY WORDS: Analytical Model, Effective moduli, Numerical Model, FEA, Flip Chip. NOMENCLATURE E Modulus of elasticity, C Volume hction, V Poisson's Ratio. a a Stress Q StiffnessMatrix E Strain Symbols AT Change in temnerature. Coefficient of t h e d expansion (CTE)