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Solder joint reliability is of great concern to semiconductor and electronic product manufacturers. Due to rapid advancements in the electronic industry, packages with fine pitch ball grid array have been increasingly used in portable electronic devices. The mechanical shock resulting from mishandling during transportation or custom usage may lead to malfunction of product. A Joint Electron Device Engineering Council (JEDEC) standard (JESD22‐B111) for a board‐level drop test of handheld electronic products was released to specify the drop test procedure and conditions in 2003. The purpose of this paper is to design and analyze the performance of a drop test apparatus created in an in‐house laboratory in terms of research basis. The specified impact shock with a sine wave accompanied by peak acceleration and pulse duration is a core requirement. The impact pulse is a complex function of various tester parameters. However, this is a unique characteristic based on the infrastructure design of each drop tester. Once the main frame of the drop tester is established, the drop height, strike surface material, and thickness are the major factors to evaluate the performance of drop tester. Therefore, many time‐consuming experimental trial‐and‐error steps are required to calibrate and characterize a drop tester to achieve the required impact pulse. The most serious conditions B, G and H are achieved, also for condition A, which satisfies the JESD22‐B111 test conditions. To provide design guidelines, the dynamic simulation using finite element model by ANSYS LS‐DYNA code was performed in terms of drop height, strike surface material, and thickness. This study observed that () the peak acceleration and pulse duration are significantly affected by strike surface thickness; () the peak acceleration is strongly affected by strike surface modulus, but less so on the pulse duration; () the drop height affects the peak acceleration, but is insignificant on the pulse duration. The results between experiment and simulation are well correlated at certain levels. An empirical relationship is developed to determine the different design parameters of peak acceleration and pulse duration. In real applications, the designed parameters that can be varied to achieve the desired impact pulse are strike surface modulus and thickness because the drop height is standard.

To meet varying requirements for a wide variety of contemporary media applications with evolving standards, a generic and flexible media-processing design platform is essential to manage increasing system-on-a-chip (SoC) design complexity with minimal design cost and time-to-market. A possible solution to the problem is combining several reconfigurable hardware resources with a programmable processor into a single-chip device such that flexibility and performance can be pursued at the same time. While several innovative reconfigurable architectures have been reported in the literature, none of these architectures are poised to provide the ease of software development for sophisticated SoC-based media processing applications. In this paper, we propose a new flexible heterogeneous multicore architecture system, which comprises a main reduced-instruction set computer (RISC) processor and a reconfigurable controller along with other configurable hardware blocks such as DSP processors or intellectual property blocks (IPBs). The key idea is that the interactions of those hardware blocks are grouped together and instructions are defined to express a middle-grained parallelism among intellectual property blocks in terms of several sequences of customized long instruction words (CLIW). A CLIW ROM is reconfigurable in response to application changes. We design the instruction set architecture, called reconfigurable controller, and show the implementation details. In addition, we demonstrate the necessary software tools that are needed to generate the suitable CLIW instruction code for applications.

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