An efficient BIST method for distributed small buffers

Jone, Wen-Ben; Huang, Der-Chen; Wu, S.C.; Lee, K.J.

doi:10.1109/tvlsi.2002.800532

Cited by 11 publications

(37 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Advances in semiconductor technology have enabled concurrent testing of embedded cores, e.g., embedded SRAMs (e-SRAMs), in a System-on-a-Chip (SoC) [1][2][3][4][5][6][7][8][9][10] as an effective approach for total test time reduction. Power consumption in test mode is known to be higher than that in a mission mode [6].…”

Section: Introductionmentioning

confidence: 99%

A retention-aware test power model for embedded SRAM

Wang

Yang

et al. 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

View full text Add to dashboard Cite

This paper addresses the test power model problem for embeddedSRAMs (e-SRAMs). Previous researches treat e-SRAMs the same as other SoC core and use a "single-rectangle" power model to describe their test power consumption. This leads to significant waste of test time since e-SRAM test usually includes a long period of "zero" power consumption for the detection of Data Retention Faults. This paper takes advantage of this "zero" power period and proposes a "retention-aware" test power model for e-SRAMs. The proposed model is evaluated and its impact on test time reduction is reported for various scenarios in terms of retention test duration, memory capacities, test algorithm complexities, etc. A formula is derived to predict the maximum test time reduction when the "zero" power period is fully utilized in a SoC environment.

show abstract

Section: Introductionmentioning

confidence: 99%

A retention-aware test power model for embedded SRAM

Wang

Yang

et al. 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

View full text Add to dashboard Cite

show abstract

“…On the other hand, a parallel Local Response Analyzer (LRA), instead of a serial response analyzer, is used to reduce the test time of these distributed small e-SRAMs. Results from our evaluations show that the proposed test architecture can achieve a better defect coverage and test time compared to those obtained in [4,5], with a negligible area cost. …”

mentioning

confidence: 88%

“…To overcome the above challenges, previous work mainly focuses on developing test architectures which support parallel BIST with a limited number of control and data signals [4][5][6][7][8][9]. In [4][5][6][7][8][9], the concurrent tests of such small distributed e-SRAMs allow a dramatic reduction in the total test time.…”

Section: Introductionmentioning

confidence: 99%

“…The improvements are mainly two-fold. On one hand, the testing of time-consuming Data Retention Faults (DRFs), that is neglected by the test architecture in [4,5], is now considered and performed via a DFT technique referred to as the "No Write Recovery Test Mode (NWRTM)". On the other hand, a parallel Local Response Analyzer (LRA), instead of a serial response analyzer, is used to reduce the test time of these distributed small e-SRAMs.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Designs for reducing test time of distributed small embedded SRAMs

Wang

Ivanov

19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings.

View full text Add to dashboard Cite

This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (e-SRAMs). This architecture improves the one proposed in [4,5]. The improvements are mainly two-fold. On one hand, the testing of time-consuming Data Retention Faults (DRFs), that is neglected by the test architecture in [4,5], is now considered and performed via a DFT technique referred to as the "No Write Recovery Test Mode (NWRTM)". On the other hand, a parallel Local Response Analyzer (LRA), instead of a serial response analyzer, is used to reduce the test time of these distributed small e-SRAMs. Results from our evaluations show that the proposed test architecture can achieve a better defect coverage and test time compared to those obtained in [4,5], with a negligible area cost.

show abstract

“…For example, when many different e-SRAMs share the same BIST engine to save silicon area, depending on the BIST scheme, they may [8] or may not [11] be able to be tested in parallel. In this paper, we consider the case that each e-SRAM is supplied with its own BIST engine.…”

Section: Related Work In Test Schedulingmentioning

confidence: 99%