No abstract

This work thoroughly explores the considerations and optimizations of dopant segregated Schottky barrier MOSFETs (DS-SBMOS) using two-dimensional device simulations. The dependences of the device characteristics on the dopant segregated layer are clarified in the DS-SBMOS. The heavier and wider dopant segregation layer efficiently modifies the Schottky barriers to suppress the off-state ambipolar conduction and simultaneously to enhance the on-state driving current. However, DS-SBMOS devices have slightly worse short-channel effects than conventional MOSFETs, because of additional segregation extensions into the silicon substrate. Importantly, apparent degradations of DS-SBMOS in ambipolar conduction are observed when a thinner gate-insulator or a heavier halo profile is used for the scaled short-channel DS-SBMOS. Dual workfunction gate (DWG) architecture is first proposed to optimize DS-SBMOS by tailoring Schottky barrier distributions through vertical gate engineering. An optimal design of DS-SBMOS devices can be achieved using the DWG structure with enhanced driving current, minimized ambipolar conduction and a suitable short-channel effect as the gate-insulator is scaled down.

No abstract

This work presents a novel Schottky barrier flash cell with promising source-side injection programming. The effects of the Schottky barrier on source-side injection programming are demonstrated by two-dimensional device simulations. The unique Schottky barrier at the source/channel interface significantly promotes the amount of source-side hot electrons to provide high injection efficiency at considerably low voltages without compromising between gate and drain biases. The new source-side injection Schottky barrier flash cell, which has a compact floating-gate structure with a metallic source/drain, is proposed for the first time as future flash memory.