Device considerations and design optimizations for dopant segregated Schottky barrier MOSFETs

Abstract

This work thoroughly explores the considerations and optimizations of dopant segregated Schottky barrier MOSFETs (DS-SBMOS) using two-dimensional device simulations. The dependences of the device characteristics on the dopant segregated layer are clarified in the DS-SBMOS. The heavier and wider dopant segregation layer efficiently modifies the Schottky barriers to suppress the off-state ambipolar conduction and simultaneously to enhance the on-state driving current. However, DS-SBMOS devices have slightly worse short-channel effects than conventional MOSFETs, because of additional segregation extensions into the silicon substrate. Importantly, apparent degradations of DS-SBMOS in ambipolar conduction are observed when a thinner gate-insulator or a heavier halo profile is used for the scaled short-channel DS-SBMOS. Dual workfunction gate (DWG) architecture is first proposed to optimize DS-SBMOS by tailoring Schottky barrier distributions through vertical gate engineering. An optimal design of DS-SBMOS devices can be achieved using the DWG structure with enhanced driving current, minimized ambipolar conduction and a suitable short-channel effect as the gate-insulator is scaled down.

Impact of Segregation Layer on Scalability and Analog/RF Performance of Nanoscale Schottky Barrier SOI MOSFET

“…From the figure it can be seen that, with increasing N DSL the Fermi-level pinning effect and the increased band bending at S/D-to-DSL interface narrows the SB width. Further, in the offstate the wider tunneling barrier for the holes at the drain reduces hole current and hence suppresses the ambipolar conduction of the device [6]. However, the narrow tunneling width for the electrons at the source increases the subthreshold leakage of the device.…”

“…Despite replacing doped S/D by metal silicides can reduce R SD , the desirability of zero Schottky barrier (SB) height at metal-semiconductor (M-S) junction formed between metal S/D and the channel is a major challenge for SB SOI MOSFETs [4][5]. In addition, ambipolar conduction and the increased subthreshold swing (S) limit the use of this device for analog/RF circuits [6].…”

“…In spite of having improved drive current due to DSL, the high frequency performance of DSSB SOI MOSFET deteriorates as compared to RSD UTB [6,8]. In order to improve the high frequency performance of this device lot of work has been carried out by different groups through experiments [9][10] and by simulations [11][12].…”

Drain-induced Schottky barrier source-side hot carriers and its application to program local bits of nanowire charge-trapping memories

“…Schottky barrier source/drain devices have shown a growing interest from the semiconductor industry because of their potentiality to remove the need of fabricating ultra-shallow doped junctions in CMOS technologies. [1][2][3][4][5][6][7] The Schottky source/drain barriers produce the particular ambipolar conduction as a strong function of gate voltage. [8][9][10][11][12][13] Both electron and hole carriers can pass through the thin Schottky barriers either at the source or drain junctions, contributing to considerable drain currents.…”

Monte Carlo Study of Dopant-Segregated Schottky Barrier SoI MOSFETs: Enhancement of the RF Performance

“…This thin, highly doped layer induces a strong band bending close to the contact enhancing the tunneling probability (and consequently also the drive current), as exemplified in [6]- [13]. Several authors have disclosed the advantages of DS layers, focusing on the reduced effective barrier height, the I -V curves, the parasitic contact resistance, the ON-OFF current ratio or the variation of the threshold voltage [6], [8], [12], [14]- [23] proving that the use of DS layers provides higher performance SB-MOSFETs for several analog and digital applications. However, few studies address the effects of the presence of a DS layer on the transconductance or cutoff frequency of SB-MOSFETs [17], [19], [24], [25].…”