Random threshold voltage (VTH) fluctuation data obtained

No abstract

We have developed scanning capacitance microscopy (SCM) with a self-sensing conductive probe that can be used to obtain static capacitance (dC=dZ) images by virtue of the vertical vibration of the probe tip. This technique for dC=dZ imaging can delineate features, such as thickness variations or fixed charge distributions, within a dielectric film and provide a lateral resolution comparable to that of simultaneously obtained topography images. In this work, we have experimentally revealed that the lateral resolution of a dC=dZ image is insensitive to the probe tip amplitude, and the sensitivity of dC=dZ images strongly depends on the distance of the gap between the probe tip and the sample surface. These results and the force-distance characteristics of the self-sensing conductive probe indicate that the dC=dZ signal is mostly determined by the probe tipsample capacitance and also that the spatial resolution of dC=dZ imaging is not affected by the surface-adsorbed meniscus layer under a vacuum environment measurement. Finally, we have demonstrated sub-10-nm spatial resoluton in dC=dZ imaging for thin dielectric film measurement.

-SONOS memory cell using a split gate structure is studied using simulations. The dependence of channel hot electron (HE) IntroductionSplit gate memory cells using source-side-injection (SSI) for programming have generated much interest recently [1][2]. SSI gives higher injection efficiency, faster programming speed and lower power consumption compared to channel hot electron (CHE) injection [1][2][3]. Most of the split gate cells studied so far use floating gate for charge storage. Using nitride for charge storage gives the additional benefits of SONOS type memories [5][6]. SONOS memories are usually programmed using CHE injection and erased using band-to-band tunnelling induced hot hole erase (HHE) for low power and multi bit operation. However, in these, the mismatch in spatial distribution of the trapped electrons and holes is a severe problem affecting the device endurance and retention [4,[8][9]. In this paper, we show through simulations that the hot electron (HE) and hot hole (HH) injection points (during program and erase, respectively) can be independently controlled by using a split gate structure. We first study the effect of trapped charge position on IV (I D -V PG ) characteristics, followed by the effect of program and erase biases on channel HE and HH profiles, respectively. Finally, the effect of program gate length and channel doping on the hot carrier profiles is studied.

No abstract