Random threshold voltage (VTH) fluctuation data obtained

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We have developed 65nmnode CMOS technology for generalpurpose systemdnaship (SoC), in which both standby and active power reductions are strongly required. With highly reliable triple gate oxide ( 1 . 3~ 1.6nm and 3.2nm) using low damage process, an average standby current can be reduced to one-fifth compared with conventional case. Gate predoping and RTA conditions were optimized to maintain oniurrent even with the supply voltage of 0.9V. Highspeed (HS) transistors show on-currcnt of 6 8 0 p N~m for nFET and 240pNpm for pFET with 5 of 13nA/pm and I , , = of 30nAipm. Low-gateieakage (LGL) transistors show on-current of 490pNpm for nFET and 1 7 5~N p m for pFET with 5 of 0 . 8 N p m and Io= of 3nA/pm. Gate oxide of all the above transistors exhibit tight TDDB distributions.

45-nm CMOS devices with a steep halo using a highramprate spike annealing (HRR-SA) are demonstrated with drive currents of 697 and 292 pA/pm for an off current less than 10 nA/pm at 1.2 V. For an off current less than 300 nA/pm, 33-nm pMOSFETs have a high drive current of 403 pA/pm at 1.2 V. In order to fabricate a steeper halo than these MOSFETs, a source/drain extension (SDE) activation using the HRR-SA process was performed after a deep source/drain (S/D) formation. By using this sequence defined as a reverse-order S/D formation, 24-nm nMOSFETs are achieved with a high drive current of 796 pA/pm for an off current less than 300 nA/pm at 1.2 V.