We have developed 65nmnode CMOS technology for generalpurpose systemdnaship (SoC), in which both standby and active power reductions are strongly required. With highly reliable triple gate oxide ( 1 . 3~ 1.6nm and 3.2nm) using low damage process, an average standby current can be reduced to one-fifth compared with conventional case. Gate predoping and RTA conditions were optimized to maintain oniurrent even with the supply voltage of 0.9V. Highspeed (HS) transistors show on-currcnt of 6 8 0 p N~m for nFET and 240pNpm for pFET with 5 of 13nA/pm and I , , = of 30nAipm. Low-gateieakage (LGL) transistors show on-current of 490pNpm for nFET and 1 7 5~N p m for pFET with 5 of 0 . 8 N p m and Io= of 3nA/pm. Gate oxide of all the above transistors exhibit tight TDDB distributions.

No abstract

For the first time, we demonstrate standard cell gate density of 3650 KGate/mm 2 and SRAM cell of 0.124 μm 2 for 32nm CMOS platform technology. Both advanced single exposure (SE) lithography and gate-first metal gate/high-k (MG/HK) process contribute to reduce total cost per function by 50% from 45nm technology node, which is unattainable by dual exposure (DE) lithography or double patterning (DP) and poly/SiON gate stack.

No abstract

We experimentally studied an impact of the surface oxide layer on quantum confinement effects (QCE) in surfaceoxide/two dimensional (2D)-Si/BOX (buried oxide) quantum well structures (SQW), using UV-Raman spectroscopy, photoluminescence (PL) method, and 2D stress simulator. UV-Raman data show that tensile strain of SQW, stressed by a thermal expansion mismatch between oxide and Si layers, decreases with decreasing the surface oxide thickness TOX. According to the strain behavior in SQW and strained-Si, PL results show that bandgap EG of the SQW rapidly expands with decreasing TOX. However, QCE in SQW keep stable in spite of high temperature postannealing process.