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We fabricated ox-FeSi 2 and 13-FeSi 2 layers by using two methods: Ion Beam Synthesis (IBS) and Molecular Beam Allotaxy (MBA). In the latter technique a trapezoidal-shaped Fe profile was embedded in the Si matrix by codeposition of Si and Fe at temperatures of about 650TC. A rapid thermal anneal of the IBS and MBA samples at 1150'C for 10 s is necessary to obtain continuous a-FeSi 2 layers. The Fe vacancy concentration of the a-FeSi 2 layers was varied by a further anneal at lower temperatures. Resistivity measurements indicate a decrease of the resistivity with decreasing Fe vacancy concentration. The a-FeSi 2 was transformed to a continuous rl-FeSi 2 layer by an anneal at 800'C for several hours. To investigate the nature of the band gap we performed absorption measurements at room temperature and 77 K. The analysis of the room temperature data revealed a direct transition at 0.84 eV and an additional indirect transition at 0.78 eV. At 77 K the direct transition shifts to -0.875 eV and the indirect to -0.86 eV.

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Boltzmann electron energy distribution poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10fold increase in drain-to-source current at 300 K. Negative Capacitance (NC) in ferroelectric materials is proposed in order to address this physical limitation of CMos technology. A polarization destabilization in ferroelectrics causes an effective negative permittivity, resulting in a differential voltage amplification and a reduced subthreshold swing when integrated into the gate stack of a transistor. the novelty and universality of this approach relate to the fact that the gate stack is not anymore a passive part of the transistor and contributes to signal amplification. In this paper, we experimentally validate NC as a universal performance booster: (i) for complementary MOSFETs, of both n-and p-type in an advanced CMOS technology node, and, (ii) for both digital and analog significant enhancements of key figures of merit for information processing (subthreshold swing, overdrive, and current efficiency factor). Accordingly, a sub-thermal swing down to 10 mV/decade together with an enhanced current efficiency factor up to 10 5 V −1 is obtained in both n-and p-type MOSFETs at room temperature by exploiting a pZt capacitor as the NC booster. As a result of the subthreshold swing reduction and overdrive improvement observed by NC, the required supply voltage to provide the same on-current is reduced by approximately 50%. Complementary Metal-Oxide-Semiconductor (CMOS) scaling will be eventually limited by the inability to remove the heat generated in the switching process 1. The origin of this issue can be traced back to the operation principle of the silicon CMOS devices governs by the non-scalability of thermal voltage (Boltzmann's tyranny). This results in preventing these devices to achieve a sub-60 mV/decade subthreshold slope (SS) at room temperature. The SS of a MOSFET is obtained by

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