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It is important to understand the distribution of recoil-implanted atoms and the impact on device performance when ion implantation is performed at a high dose through surface materials into single crystalline silicon. For example, in ultralarge scale integration impurity ions are often implanted through a thin layer of screen oxide and some of the oxygen atoms are inevitably recoil implanted into single-crystalline silicon. Theoretical and experimental studies have been performed to investigate this phenomenon. We have modified the Monte Carlo ion implant simulator, UT-Marlowe (B. Obradovic, G. Wang, Y. Chen, D. Li, C. Snell, and A. F. Tasch, UT-MARLOWE Manual, 1999), which is based on the binary collision approximation, to follow the full cascade and to dynamically modify the stoichiometry of the Si layer as oxygen atoms are knocked into it. CPU reduction techniques are used to relieve the demand on computational power when such a full cascade simulation is involved. Secondary ion mass spectrometry (SIMS) profiles of oxygen have been carefully obtained for high dose As and BF2 implants at different energies through oxide layers of various thicknesses, and the simulated oxygen profiles are found to agree very well with the SIMS data.

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This paper presents interesting results of electroplating semiconductor surfaces having adjacent p-type and n-type areas, using dc and periodic reverse ͑PR͒ voltages. It is shown that, the n-type ͑p-type͒ areas of n-type substrates having diffused/implanted p-type pockets get selectively plated by dc ͑PR͒ plating voltages. On the other hand, a dc plating voltage selectively plates the p-type areas of p-type substrates containing diffused/implanted n-type regions; in this case, PR plating serves no useful purpose. Applications of these results are discussed. © 2002 The Electrochemical Society. ͓DOI: 10.1149/1.1491983͔ All rights reserved. It is well known that both dc and pulse currents have been used for electroplating.1-8 The voltage waveform employed in pulse plating applications is shown in Fig. 1. The voltage periodically switches between two values V 1 and V 2 . When one of these two values is negative, the plating process is referred to as periodic reverse or PR plating. DC plating can be regarded as a special case of pulse plating with V 1 ϭ V 2 .In a general pulse plating application, the metal deposition rate depends on the average current over the plating waveform cycle, rather than the current levels in individual half-cycles. The average current into any area of the substrate depends on the resistance from the anode to the cathode contacting that area. Since this resistance is a function of the substrate surface condition, surface areas differing in conditions draw different average currents and plating thicknesses. Ensuring uniform plating thickness over the substrate surface, by overcoming variation in surface conditions, has been an overriding concern in electroplating research. One of the reasons for using a pulse rather than dc plating voltage is that pulse voltage can suppress plating thickness nonuniformity. [1][2][3][4][5] In contrast, this paper deals with an application wherein nonuniform plating thickness induced by surface condition variations is a desirable feature.Electroplating is the commonly used method of fabricating metal contacts of thickness Ͼ2 m on semiconductor substrates. This paper presents the interesting plating nonuniformities introduced by dc and PR plating waveforms on semiconductor substrates in which the doping polarity varies over the semiconductor surface. Both n-type substrates with p-type pockets and p-type substrates with n-type pockets are considered. Some useful applications of such plating nonuniformities are described. n-Type Substrate Having p-Type PocketsThe electroplating of these substrates is illustrated in Fig. 2. The parallel paths to the n-regions, denoted X, have been effectively represented by a single bath resistance R N in the equivalent circuit. This resistance and the bath resistance R P into the p region are inversely proportional to the surface areas of the n and p regions, respectively, exposed to the bath. The path Y encounters, in addition to R P , a p-n diode, which is absent in the path X. Note that the equivalent circuit shown applies, ev...

Ion implantation is a critical technology in semiconductor Ultra Large Scale Integration (ULSI). Binary collision approximation (BCA)-based Monte Carlo (MC) ion implantation simulators are commonly used to predict the impurity and damage profiles. A deterministic propagator is needed in these simulators to simulate the propagation of ions in crystalline materials. A search-for-target algorithm is frequently called to determine the collision partners and collision parameters in a deterministic propagator, and this is usually the computational bottleneck of MC ion implantation simulators. The standard search-for-target algorithm has been redesigned for computational efficiency and for economic usage of memory. Instead of searching for collision partners in a standard 29-atom crystal neighborhood identical to all ions, narrowed-down potential target lists are pre-computed based on the ion's relative position to a reference point as well as its direction of motion. The American National Standards Institution (ANSI) C++ standard container class bitset [1] is used to store such potential target lists, and the memory usage is very efficient. Combined with a quasi-simultaneous collision algorithm, the CPU times for MeV P and B implantation simulations are found to be reduced by more than a factor of two, rendering very reasonable computation times for MeV ion implantation simulations on standard workstations.