SRAM based reprogrammable FPGAs are sensitive to radiation-induced Single Event Upsets (SEU), not only in their user flip-flops and memory, but also in the configuration memory. Appropriate mitigation has to be applied if they are used in space, for example the XTMR scheme implemented by the Xilinx TMRTool and configuration scrubbing. The FLIPPER fault injection platform, described in this paper, allows testing the efficiency of the SEU mitigation scheme. FLIPPER emulates SEU-like faults by doing partial reconfiguration and then applies stimuli derived from HDL simulation (VHDL/Verilog test-bench), while comparing the outputs with the golden pattern, also derived from simulation. FLIPPER has its Device-Under-Test (DUT) FPGA on a mezzanine board, allowing an easy exchange of the DUT device. Results from a test campaign are presented using a design from space application and applying various levels of TMR mitigation.

A fault injection tool for Virtex FPGAs based on the fault emulation technique is presented. It allows to inject faults in the configuration control mechanism differently from the tools developed so far, which address only configuration memory cells and user registers. This permits a more realistic and complete study of device behaviour, especially in those applications in which the system operating in a harsh environment undergoes frequent reconfigurations. Injection is performed by modifying the configuration bitstream while this is loaded into the device, without using standard synthesis tools or available commercial software, such as Jbits or similar. This makes our tool independent of the system used for design development and allows a quick fault injection. Moreover, any register of the configuration state machine can be accessed and the effect of SEUs on them analyzed. This analysis is fundamental before performing radiation ground testing of this kind of devices.

This paper presents a strategy of investigation of SEU upset mechanisms in the configuration logic of Virtex I devices. Measurement procedures specifically addressing configuration logic and a hardware set up for radiation testing are described. The results of a heavy ion radiation test are then presented. Previously unreported failure mechanisms have been observed and classified and their corresponding cross sections measured.Index Terms-Field programmable gate arrays (FPGA), heavy ion radiation effects, radiation effects, semiconductor device radiation testing, single event effects.

A signal processing hardware platform has been developed for the Low Frequency Aperture Array component of the Square Kilometre Array (SKA). The processing board, called an Analog Digital Unit (ADU), is able to acquire and digitize broadband (up to 500[Formula: see text]MHz bandwidth) radio-frequency streams from 16 dual polarized antennas, channel the data streams and then combine them flexibly as part of a larger beamforming system. It is envisaged that there will be more than 8000 of these signal processing platforms in the first phase of the SKA, so particular attention has been devoted to ensure the design is low-cost and low-power. This paper describes the main features of the data acquisition unit of such a platform and presents preliminary results characterizing its performance.

The signal processing firmware that has been developed for the Low Frequency Aperture Array component of the Square Kilometre Array (SKA) is described. The firmware is implemented on a dual FPGA board, that is capable of processing the streams from 16 dual polarization antennas. Data processing includes channelization of the sampled data for each antenna, correction for instrumental response and for geometric delays and formation of one or more beams by combining the aligned streams. The channelizer uses an oversampling polyphase filterbank architecture, allowing a frequency continuous processing of the input signal without discontinuities between spectral channels. Each board processes the streams from 16 antennas, as part of larger beamforming system, linked by standard Ethernet interconnections. These are envisaged to be 8192 of these signal processing platforms in the first phase of the SKA so particular attention has been devoted to ensure the design is low cost and low power.