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The change in resistivity and composition of WSi~ films is studied. The following facts are observed. The resistivity of CVD WSix films which are more than 1000]~ thick reaches a maximum at an annealing temperature ranging from 500 ~ to 600~ Logarithmical resistivities before and after 1000~ annealing have a linear relation to the film composition. The ratio of change in resistivity between the as-deposited state and after 1000~ annealing becomes larger as the composition changes, i.e., the Si/W ratio becomes smaller and reaches the stoichiometric value. CHANGES IN RESISTIVITY 1479The change in composition between the as-deposited state and after 1000~ annealing becomes larger as the film become richer in Si. Excess Si, which is generated by annealing, segregates into the boundary between WSi~. and poly-Si. A decrease in film thickness of about 15% after 1000~ annealing is observed for WSi~.4 on SIO2. This value is smaller than the calculated value.Fluorine and hydrogen are contained in the films on the order of 10~-102~ cm -3 and 102~ cm -3, respectively. Fluorine diffuses into the gate SiO2 by annealing. From this fact, it is assumed that degradation of gate SiO2 in terms of dielectric breakdown strength can occur. ABSTRACTFactors that influence the etching properties of LPCVD deposited polysilicon were investigated. These included pressure, power, CCI4 concentration, surface preparation, polysilicon doping, mask angle, mask material, and mask aspect ratio. Organic mask etch rate was found to depend on the type of resist (PMMA, PCMS, AZ1470), while resist preparation and mask aspect ratio were seen to influence the etch profiles. We were able to obtain vertical etch profiles using inorganic masking (Si3N4). A new phenomenon of transition from anisotropic to nonanisotropiC etching was observed when the height-to-gap-width aspect ratio of the organic masks became greater than 6: i. The degree of negative undercut became more severe with increasing aspect ratio. ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 131.211.208.19 Downloaded on 2015-03-15 to IP

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Two novel contact engineering methods have been developed for submicron contact openings. The two methods, abbreviated as SCOPE (Simultaneous Contact and Planarization Etch) and PACE (Planarization After Contact Etch), interchange the process sequences of dielectric planarization and contact etch to achieve uniform contact etch. Both etching processes eliminate the need for oxide reflow, thereby minimizing the thermal budget after source/drain formation. Since the dielectric is planarized either during the contact etch (e.g., with SCOPE) or after contact etch (e.g., with PACE), the need for extensive overetching of the oxide due to the dissimilar contact depths is also eliminated. As a result, contact resistance and leakage currents are significantly reduced in comparison to results obtained with dielectrics planarized before etching. In addition, etching of field oxide due to pattern misalignment is minimized since the contacts are of similar depth.

One of the challenges in VLSI fabrication is to design submicron multilevel metals with high yield. This paper describes a concurrent engineering methodology that provides semiconductor engineers and VLSI circuit designers with an efficient test, modeling,