A 6-GHz low power SiGe direct digital synthesizer (DDS) is reported. This paper discusses the BiCMOS design improvements used for the phase accumulator and the phase-toamplitude conversion in order to achieve higher speed operation and lower power consumption compared to existing DDS. The phase accumulator is based on a three-level BiCMOS logic, and the phase-to-amplitude conversion is completed through a bipolar differential pair. The circuit has been processed in a BiCMOS SiGe:C 0.25 µm technology. The power consumption is 308 mW and it operates from a 2.8 V supply. The chip core area is 1 mm 2 .

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A 3 bits -0.25 µm BiCMOS SiGe:C accumulator operating up to 15 GHz clock frequency is presented. It is based on a high-speed and low-power three-levels BiCMOS logic which is used to implement the 1 bit full-adder and the D-flip-flop latch-up register. With this technique, the dissipated power is reduced by 30% over the usual four-levels series logic. The circuit integrates 203 (without buffers, 230 with) transistors and dissipates 67 mW (without buffers, 119 with) from a 2.7 V supply.