Two specific design methods of frequency multipliers are presented. The first one is CAD oriented and based on the "Substitute Generator Technique" using nonlinear device models. The second one is based on a novel time-domain load-pull setup to measure and optimize voltagekurrent waveforms at both ports of frequency multipliers. These complementary design approaches allow to quickly and accurately determine all the optimum operating conditions for any frequency multiplier. The first design methodology is applied to the optimization of a broadband (34.5-39)GHz PHEMT MMIC tripler integrated into a transceiver manufactured at the UMS foundry. In the same way, the time-domain loadpull characterization is applied to the optimization of a S-band HBT doubler.

No abstract

No abstract

The packaged MMIC design and measured performance of a High Linearity and Low Noise Amplifier from 12 to 30GHz are reported in this paper. A mature 0.25,um gate length Low Noise Pseudomorphic HEMT technology has been used with a BCB-based protection allowing easy and high reliability chip integration into plastic packages. A standard plastic QFN SMD package has been successfully used: 25dB typical gain has been measured with less than 2.0 dB noise figure in all the frequency band from 12 to 30GHz and more than 26dBm Output IP3 has been measured in the 18-26GHz frequency band.

No abstract