No abstract

In this paper, three-stage operational transconductance amplifiers (OTAs) for use in switchedcapacitor (SC) circuits using nanometer CMOS technologies are described. Two three-stage OTAs, one with nested-Miller compensation (NMC) as a basic compensation scheme and another with damping factor control frequency compensation (DFCFC) as an advanced compensation scheme are presented. The open-loop small-signal analysis as well as the large signalanalysis for both OTAs are investigated and their speed performance is compared and discussed. Circuit level simulations are carried out using a 90 nm CMOS technology with HSPICE. Simulation results show that the NMC and the DFCFC OTAs achieve a settling time of 17.5 ns and 8.4 ns with 0.02% accuracy, respectively, while consuming 3 mW from a 1.2 V power supply and have the same input-referred thermal noise.

In this paper, a three-stage class AB operational transconductance amplifier (OTA) with large slew rate is presented. The reversed nested Miller compensation technique is used to stabilize the proposed OTA, allowing the slew rate enhancement to be achieved by using class AB input and output stages. A flipped-voltage follower cell in the first stage in combination with a switched-capacitor level shifter in the last stage are utilized to implement the class AB operation. Circuit level simulation results are provided using HSPICE and a 90 nm CMOS technology which show 306 % enhancement in the large-signal FoM with approximately the same power dissipation compared to the class A OTA. The achieved settling time with 0.02 % accuracy for the proposed class AB and conventional class A OTAs are 7.5 and 15.3 ns, respectively.