The stains on the pad caused by polishing by-products can be observed in a copper chemical and mechanical polishing ͑CMP͒ process. In this study, the effects of stains on CMP performance such as erosion, dishing, and nonuniformity were evaluated as a function of the degree of stains accumulated on the pad. The stains on the pad deteriorate the nonuniformity of removal rate and result in the increase in erosion and dishing. CMP by-products adhere on both pores and grooves of the pad and block the flow of slurry through the grooves, resulting in the deterioration of nonuniformity. The selectivity ͑ratio of removal rate, Cu to TaN or dielectric film͒ is important in order to minimize erosion. When wafers were polished on a stained pad, the removal rate of Cu decreased ϳ30% due to the poor slurry distribution and the selectivity decreased more than 40% because the mechanical abrasion was enhanced by the presence of by-products on pad surfaces. The lower the selectivity, the higher the level of erosion on the polished patterned wafers. The higher frictional force on a stained pad results in higher temperature and etch rate of Cu which might be the reason for recess and dishing of Cu lines. The rapid scaling of metal-oxide-semiconductor field-effect transistors ͑MOSFETs͒ has been successfully continued for more than three decades since the early 1970s.1,2 In the past, these improvements were achieved mainly from the front-end process, such as reducing the transistor dimension as well as the thickness of gate oxide. Little attention was paid to the back-end of line ͑BEOL͒ multilevel interconnects. Because of the scaling of BEOL, resistance and capacitance ͑RC͒ delay cannot catch up with the improvement of transistors, and multilevel interconnects are rapidly becoming a bottleneck to overall performance. 3 The use of new materials for interconnects will reduce the RC delay. Copper application for interconnection offers faster and more reliable integrated circuit ͑IC͒ device due to its low electrical resistivity and superior electromigration resistance compared to aluminum. By replacing Al with Cu, there is a 40% reduction in resistance. 4 For Cu interconnection, a damascene process using chemical mechanical polishing ͑CMP͒ has been introduced and Cu CMP has been actively investigated in recent years.5 CMP is a process of polishing assisted by chemical and mechanical reactions. Especially, the performance of Cu CMP is strongly dependent on the slurry chemistry because Cu easily corrodes and does not form a thick Cu oxide on Cu surface. 6During Cu CMP process, polish by-products are usually found on the polishing pad. The polish by-products are generated by the chemical interaction between the Cu film on the wafer surface and the slurry. The polish by-products cannot be easily removed by simple pad conditioning using a diamond disk, and the color of the pad is changed to brown after Cu CMP. Many semiconductor manufacturers have been using a special pad-cleaning solution to eliminate the stains on the pad, but it cannot re...

This paper attempts to establish planarization model in chemical mechanical polishing of silicon oxide using high selective ceria slurry. Though removal rate of the high area is increased due to a high pressure focused on the area with abrasive and pad, the removal rate of the same area is not increased but decreased even in the very beginning of polishing with ceria slurry. It also observed that only the elevated area is polished and dishing is not occurred during the polishing in high selective ceria CMP. In this work, it is proposed that ceria abrasives are filled in the low trench area and then support the pad as well as high area during the CMP, which results in planarization without dishing.

The effects of surfactants on oxide-to-polysilicon selectivity during chemical mechanical polishing have been investigated. Slurries with nonionic surfactants such as Brij surfactants, polyethylene oxide ͑PEO͒, and ethylene oxide-propylene oxide-ethylene oxide triblock copolymer enhanced oxide-to-polysilicon polishing selectivity. Although a current conventional oxide slurry has a low oxide-to-polysilicon selectivity of 0.5:1, slurries with nonionic surfactants show a higher selectivity due to a combined effect of adsorption and interfacial adhesion of added nonionic surfactant molecules on the polysilicon surface. The oxide-to-polysilicon selectivity of the Brij surfactant added slurry displayed a stronger dependency on the hydrophile-lipophile-balance ͑HLB͒ value than the type of alkyl group or the chain length of surfactants. Especially, Brij52 with low HLB value gave an oxide-to-polysilicon selectivity of 9.3, which is 17 times higher than the selectivity of a commercial oxide slurry. A high molecular weight polymeric surfactant such as PEO also gave a greater selectivity than a low molecular weight surfactant. In addition, slurries with nonionic surfactants reduce the final thickness variation effectively in damascene structure having a polysilicon stopping layer. The final thickness variation polished with the Brij52 added slurry was decreased to one fourth of that with the conventional oxide slurry only.As the design rule decreases in semiconductor manufacturing industry, multilayer integration using chemical mechanical polishing ͑CMP͒ is being widely adopted to obtain a flat surface during processing. Current CMP processes are focused on meeting a higher planarity and uniformity requirements. As a result, the process windows of CMP processes become tighter. 1-5 In general, high selective slurry to a stopping layer is required to obtain these performances simultaneously. When a high selective slurry is used, effective stop on a stopping layer becomes possible due to the high selectivity of materials. Typical examples of selective polishing with highly selective slurry are shallow trench isolation CMP process with silicon nitride stopper and copper CMP process with tantalum ͑Ta͒ or tantalum nitride ͑TaN͒ stopping layer. 1-7 The concept of selective CMP process is important especially in a damascene structured pattern. When a single material is polished to planarize an oxide layer like interlayer dielectric ͑ILD͒ or intermetal dielectric ͑IMD͒, the selectivity is not critical. 1-4 However, the selectivity to the stopper material is indispensable for uniformity and planarity when two or more materials are polished simultaneously.Polysilicon is one of the candidates as a stopping material for a damascene structure. CMP process with efficient stop on polysilicon requires a improved selective slurry to polysilicon. However, the current conventional oxide slurry composed of fumed silica abrasive does not stop effectively on polysilicon due to the low oxide-topolysilicon polishing selectivity of 0.5:1. To increase...

PVC (Passive Voltage Contrast) fault isolation method by using a SEM (Scanning Electron Microscope) has been widely used for isolating the defective mc (metal contact) in the CMOS logic SRAM bit cell array. The low power (LP) processed sram cells are easy to charging under PVC test and it helps isolating defective contacts in the cell. However, some device such as a high speed (HS) sram cell is hard to charging in PVC test by unknown reason. It makes difficulties for isolating defective contacts in the sram cell array. In this paper, our group analyzed the electrical current of each contact in sram cell using a nanoprobing technique and correlated it with PVC charged contact images, respectively. Also, the difference of PVC charging status between LP and HS SRAM are characterized electrically by using a nanoprober. The nanoprobing result indicates that a slight increasing a leakage current of about 10pA can abruptly change the charging brightness from dark to grey. Finally, we can found some clues for making grey contacts of HS SRAM using not only a nanoprobing but also a HRTEM (High Resolution Transmission Electron Microscope) image.

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