No abstract

Conventional flip chip on board processing involves four major steps: flux application, solder reflow, underfill flow, and underfill cure. The latter two steps are particularly time consuming. To address this issue, a new flip chip process has been developed in which underfill is dispensed prior to chip placement or directly on the wafer and solder reflow and underfill cure occur simultaneously. This reduces the cycle time required for manufacturing. However, the presence of the underfill can affect the flip chips’ capacity for self-alignment. Self-alignment occurs in controlled collapse bonding when the solder interconnects become liquidus and, driven by surface tension, pull the chip into registration with the substrate. To study flip chip self-alignment in the presence of underfill, the viscous forces acting on the chip during realignment are modeled after Couette flow and the overall system is modeled as a spring-mass-damper. This paper details the modeling process and includes parametric studies to predict those conditions that are more conducive to alignment, as well as those which are not.

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

No abstract

The industry has witnessed the adoption of the flip chip for its low cost, small form factor, high performance, and great I/O flexibility. As three-dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon-to-silicon assembly, is gaining more and more popularity.No flow underfill is of special interest for the wafer level flip chip assembly, as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would otherwise be necessary for the standard capillary underfill process. This paper introduces the development of a no flow underflll process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underflll reflow proflle study, underfill dispense amount study, chip floating control, underfill voiding reduction, and yield improvement. Also, different no flow underfill candidates were investigated to determine the best performing processing material. Keywords-Noflow underflll, flip chip, wafer level packaging, silicon to/on silicon, chip floating, underfill voiding