We propose a method to evaluate the carrier transport properties in the inversion layer of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) experimentally. Our approach differs from conventional methods, which have adjusted the parameters in conventional mobility models. Intrinsic phonon-limited mobility (μ phonon ) in the SiC MOSFET was observed by suppressing the severe impact of Coulomb scattering on the SiC MOS inversion layer by lowering the acceptor concentration (N A ) of the p-type well region to the order of 10 14 cm −3 . In this study, we investigated the carrier transport properties in the inversion layer of Si-face 4H-SiC MOSFETs with nitrided oxide. It is revealed that the μ phonon of the SiC MOSFET is a quarter or less than the conventionally presumed values. Additionally, surface roughness scattering is found not to be the most dominant mobility-limiting factor even at high effective normal field (E eff ) for the SiC MOSFET. These results demonstrate that conventional understanding of carrier scattering in the SiC MOS inversion layer should be modified, especially in the high E eff region.

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Ensuring gate oxide reliability and low switching loss is required for a trench gate SiC-MOSFET. We developed a trench gate SiC-MOSFET with a p-type region, named Bottom P-Well (BPW), formed at the bottom of the trench gate for bottom oxide protection. We can see an effective reduction in the maximum bottom oxide electric field (Eox) and a significant improvement in dynamic characteristics with a grounded BPW, whose dV/dt is 76 % larger than that with a floating BPW due to reduction in gate-drain capacitance (Cgd). The grounded BPW is found to be an effective means of both suppressing Eox and reducing switching loss.

We evaluate the stacking faults (SFs) expansion from basal plane dislocations (BPDs) converted into threading edge dislocations (TEDs) under the current stress to the pn devices and analyzed the nucleation site of the SF by combined polishing, chemical etching in molten KOH, photoluminescence imaging, Focus ion beam, transmission electron microscopy, and Time-of-Flight secondary ion mass spectrometer techniques. It was found that the formation of SFs occurs upon the current stress levels of 400 A/cm2 where the diode area is not including BPDs in the drift layer after the high current stress, and the high current stress increases the SFs expansion density. It was also found the dependence of the junction temperature. The estimated activation energy for the expansion of SFs is Ea = 0.46 eV. The SF extends from the conversion point of the BPD into the TED within buffer layer. Even though BPDs converted into TEDs within the high doped buffer layer, SFs expand under high current stress.

We have successfully developed 4H-SiC devices including metal–oxide–semiconductor field-effect transistors (MOSFETs) and Schottky barrier diodes (SBDs) with a rated voltage of 3.3 kV. The conduction loss of the SiC-MOSFET was reduced to as low as that of the Si-insulated gate bipolar transistor (IGBT) by the n-type doping of the junction field-effect transistor region (JFET doping). The JFET doping technique is effective in reducing the temperature coefficient of resistance in the JFET region, leading to the decreased on-resistance of the SiC-MOSFET at high temperatures. These devices have been applied to 3.3 kV/1500 A modules for the world’s first all-SiC traction inverter. The switching loss of the new traction inverter system is approximately 55% less than that of a conventional inverter system incorporating Si modules.