Bias temperature-dependent characteristics of nanoscale silicon-oxide-nitride-oxide-silicon memories are investigated under program/erase (P/E) Fowler–Nordheim (FN) stresses. In the erased cell, FN stress time evolution is found to be a similar physical process to the recovery of interface traps (NIT) that takes place under the dynamic negative bias temperature instability stress. In addition, anode hole injection induced holes are trapped in the bottom oxide, both in the erase and in the read conditions of the erased cell, and make significant roles in the reverse hysteresis and higher power-law exponent n at higher temperature in P/E cycled erased cells. While the temperature-independent n=0.3 is observed in the programed cell, the temperature-sensitive n=0.36–0.66 is observed in the erased cell.

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Extracting the trap distribution in charge trapping layers of charge trap flash memory devices, an optical C-V method (OCVM) is proposed. Applying photons with λ=532nm to the oxide-nitride-oxide layer with 50∕60∕23Å in metal-oxide-nitride-oxide-semiconductor charge trap flash devices, the trap density in the charge trapping nitride layer is extracted to be 1.16×1018–1.67×1019cm−3eV−1 over the energy EC−Et=1.36–1.64eV. Combining sub-band-gap photons in C-V characterization, the OCVM method is free from the thermal and electrical stresses which are inherent in conventional characterization methods even though they are critical error factors for accurate characterization of charge trapped flash memory devices.

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