In this paper, a multilevel inverter based on cascade connection of new submultilevel inverters is presented. The suggested submultilevel inverter is constructed using series connection of basic switching units. The proposed multilevel inverter uses fewer power switches in comparison with some similar topologies which results in reduction of switch gate drivers and also converter size and cost. The proposed multilevel inverter can be implemented in both symmetric and asymmetric configurations. The multilevel inverter configuration and operation principle are described in detail, and then, design methods of symmetric and asymmetric configurations are given. Determination of the optimal number of basic units and cascaded submultilevel inverters regarding criteria such as number of switches and total blocking voltage (TBV) of switches is studied. Power losses of the proposed multilevel inverter are calculated, and then, its symmetric and asymmetric configurations are compared with each other and also with similar cascaded multilevel inverters in various items. The validity of the suggested cascaded multilevel inverter is verified using both computer simulations and laboratory prototype implementation.KEYWORDS cascade connection, inverter, multilevel, submultilevel | INTRODUCTIONCascaded multilevel inverters are one of the multilevel inverter categories that are constructed using a series connection of several single-phase inverters. These structures generate medium-voltage levels using only standard low-voltage mature technology components. Cascaded multilevel inverters also feature a high modularity degree because each inverter is considered as a module with similar circuit topology. 1 Numerous researches have been devoted to modifying previous cascaded multilevel inverters from switching devices number, switches blocking voltage, DC voltage source number, power losses, and output voltage THD points of view. A single-phase, nine-level, cascaded multilevel inverter has been introduced in Odeh Ch and Nnadi. 2 To generate the gating signals for the inverter power switches, a phase disposition multicarrier PWM scheme is applied. In Belkamel et al, 3 a new topology of three-phase cascaded multilevel inverter with asymmetric configuration has been presented which is composed of series-connected submultilevel inverter units. The main merit of the introduced multilevel inverter is reduction in the number of switches, switch gate driver circuits, switch blocking voltage, installation area, and total cost. Another structure for cascaded multilevel inverter has been presented in Kangarlu and Babaei, 4

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This study proposes a multilevel inverter with optimised structure from switching device number point of view. Configuration of the presented multilevel inverter is modular and extendable. Three different methods are introduced to determine the magnitude of DC voltage sources. Characteristics of inverter topology based on suggested methods are given and compared with each other. Also, the proposed multilevel inverter is compared with some similar topologies in terms of controlled switches, driver circuits, DC voltage sources and total blocking voltage to verify its advantages and probable disadvantages where the results show the superiority of the proposed topology in the comparison items. Selective harmonic elimination pulse width modulation technique is applied to achieve output voltage with high quality. Finally, a laboratory prototype of the proposed multilevel inverter is implemented and then, the experimental and simulation results are derived to validate the inverter capability in generating staircase waveforms.

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