In the hardware design of Battery Energy Storage System (BESS) interface, in order to meet the high voltage requirement of grid side, integrating 10 kV Silicon-Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) into the interface could simplify the topology by reducing the component count. However, the conventional gate driver design is challenging and inextensible in BESS, since the high voltage rating and high dv/dt bring the requirements of high voltage isolation and low common-mode capacitance. Therefore, in this paper, a scalable converter-based self-powered (SCS) gate driver is further proposed. A 5 kV-input power extracting converter based on a voltage-balanced SiC MOSFET stack is constructed to self-power the gate driver, which exhibits simplification of basic topology and sufficient gate driver power handling capability regardless of the switching requirement of main loop power device. Besides this, the power extracting converter is designed to act as a clamping Resistor-Capacitor-Diode (RCD) snubber circuit, which makes the SCS gate driver scalable to the series connection of power devices. Analysis and design consideration are given in detail, followed by the experimental verification using 10 kV/10 A SiC MOSFETs.

In high-power medium-voltage applications, inductors usually have multiple windings on a single core, due to the high inductance value and high current stress. The multiple coils are electronically connected in either series or parallel, with considerations of windings loss and cost. However, the differences in parasitic capacitance of inductors using parallel and series connections are not discussed. Therefore, this paper reveals that compared with using parallel connections, using series connections for windings can significantly reduce the parasitic capacitance in multi-windings inductors without sacrificing the power density and adding manufacturing complexities. Physics-based models of parasitic capacitance in inductors with round-cable and copper-foil are developed for theoretical analysis. According to the theoretical analysis, the equivalent capacitance contributed by the stored electric field energy between two layers can be halved at least. The theoretical analysis is also verified by FEM simulations. Six prototyped inductors are also experimentally compared to validate the theory.

<b>This paper rethinks the basic assumptions often used in analytically modeling parasitic capacitance in inductors. These assumptions are classified in two commonly-used physics-based analysis methods: the lumped capacitor network method and the energy conservation method. The lumped-capacitor network method is not the proper solution for calculating the equivalent parasitic capacitance in inductors at the first resonant frequency, but rather represents the equivalent parasitic capacitance above the last resonant frequency. The energy-conservation based method is shown to be more accurate and a reasonable solution to model the equivalent parasitic capacitance at the first resonant frequency. Multiple case studies of inductors are used for verifying the theory. </b>

This paper rethinks the basic assumptions often used in analytically modeling parasitic capacitance in inductors. These assumptions are classified in two commonly-used physicsbased analysis methods: the lumped capacitor network method and the energy conservation method. The lumped-capacitor network method is not the proper solution for calculating the equivalent parasitic capacitance in inductors at the first resonant frequency, but rather represents the equivalent parasitic capacitance above the last resonant frequency. The energy-conservation based method is shown to be more accurate and a reasonable solution to model the equivalent parasitic capacitance at the first resonant frequency. Multiple case studies of inductors are used for verifying the theory.

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