This paper proposes a general physics-based model for identifying the parasitic capacitance in medium-voltage (MV) filter inductors, which can provide analytical calculations without using empirical equations and is not restricted by the geometrical structures of inductors. The elementary capacitances of the MV inductor are identified, then the equivalent capacitances between the two terminals of the inductor are derived under different voltage potential on the core. Further, a three-terminal equivalent circuit, instead of the conventional two-terminal equivalent circuit, is proposed by using the derived capacitances. Thus, the parasitic equivalent capacitance between the terminals and core are explicitly quantified. Experimental measurements for parasitic capacitances show a good agreement with the theoretical calculations. Index terms-Physics-based modeling, parasitic capacitance, medium-voltage, filter inductors, three-terminal equivalent circuit.This work is supported by MV-BASIC project (https://www.mvbasic.et.aau.dk/), which is co-funded by the

Support has been received from the IEPE and APETT projects funded by Innovation Fund Denmark and the MV platform project funded by the Obel Family Foundation.

This paper characterizes three parasitic capacitances in copper-foiled medium-voltage inductors. It is found that the conventional modeling method overlooks the effect of the fringe field, which leads to inaccurate modeling of parasitic capacitances in copper-foiled inductors. To address this problem, the parasitic capacitances contributed by the fringe electrical field is identified first, and a physics-based analytical modeling method for the parasitic capacitances contributed by the fringe electrical field is proposed, which avoids using any empirical equations. The total parasitic capacitances are then derived for three different cases with three different core potentials, from which a three-terminal equivalent circuit is derived, and thus, the parasitic capacitances in copper-foiled inductors are explicitly identified. The calculated results show a close agreement with the measured capacitance by using an impedance analyzer. Two recommendations for reducing the parasitic capacitances in copper-foiled inductors are given in this paper.

Medium voltage 10 kV Silicon Carbide MOSFETs, introduce challenges regarding converter design. Very high rate of voltage change and capacitive couplings to for example cooling systems cause increased electromagnetic interference. The aim of this paper is to accurately model the capacitive coupling to a heat sink and experimentally validate the model. An analytic model of the heat sink is developed which is demonstrated to be in excellent agreement with experimental results. The experimental result validates the modelled heat sink network allowing engineers to choose a suitable grounding impedance to comply with the electromagnetic compatibility regulations. Common mode current mitigation for Medium Voltage Half Bridge SiC Modules CHRISTENSEN Nicklas EPE'17 ECCE Europe ISBN: 9789075815276 et CFP17850-ART P.1

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