Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM

Jørgensen, Asger Bjørn; Christensen, Nicklas; Dalal, Dipen Narendra; Sonderskov, Simon Dyhr; Bęczkowski, Szymon; Uhrenfeldt, Christian; Munk‐Nielsen, Stig

doi:10.23919/epe17ecceeurope.2017.8098962

Cited by 41 publications

(34 citation statements)

References 14 publications

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“…This model is denoted as a Level 1 model, and self-inductance calculated for each trace is shown in Table II. A reported issue of this is that the summation of the inductances becomes large, because when evaluating each inductance individually, no mutual inductance effects are included in the model [42]. Thus, often an approach is used at which the full loop is evaluated [30], [43], [44]. In this approach, each device is modeled as a conductor, i.e., the drain and source of a switch are electrically shorted.…”

Section: Electrical Simulation Modelmentioning

confidence: 99%

A Fast-Switching Integrated Full-Bridge Power Module Based on GaN eHEMT Devices

Jørgensen

Bęczkowski

Uhrenfeldt

et al. 2019

IEEE Trans. Power Electron.

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New packaging solutions and power module structures are required to fully utilize the benefits of emerging commercially available wide bandgap semiconductor devices. Conventional packaging solutions for power levels of a few kilowatt are bulky, meaning important gate driver and measurement circuitry are not properly integrated. This paper presents a fast-switching integrated power module based on gallium nitride enhancementmode high-electron-mobility transistors, which is easier to manufacture compared with other hybrid structures. The structure of the proposed power module is presented, and the design of its gate driver circuit and board layout structure is discussed. The thermal characteristics of the designed power module are evaluated using COMSOL Multiphysics. An ANSYS Q3D Extractor is used to extract the parasitics of the designed power module, and is included in simulation models of various complexities. The simulation model includes the SPICE model of the gallium nitride devices, and parasitics of components are included by experimentally characterizing them up to 2 GHz. Finally, the designed power module is tested experimentally, and its switching characteristics cohere with the results of the simulation model. The experimental results show a maximum achieved switching transient of 64 V/ns and verify the power loop inductance of 2.65 nH.

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Section: Electrical Simulation Modelmentioning

confidence: 99%

A Fast-Switching Integrated Full-Bridge Power Module Based on GaN eHEMT Devices

Jørgensen

Bęczkowski

Uhrenfeldt

et al. 2019

IEEE Trans. Power Electron.

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“…One such module with external SiC JBS diodes is presented in Fig. 7 along with the schematic displaying the power module parasitics extracted form ANSYS Q3D [4]. The shown power module is packaged in-house at Aalborg University and populated with two generation 1 10 kV/10 A SiC MOSFET and 10 kV SiC JBS diode dies from Wolfspeed.…”

Section: Device Under Testmentioning

confidence: 99%

“…With latest technological improvements these devices are reaching the level of maturity to be considered for medium voltage and high power conversion applications e.g., solid state transformer [2]. Considering high dv/dt switching transients, intrinsic device parasitics together with parasitic capacitance external to the device are crucial and require careful optimization to utilize SiC MOSFETs at their full potential [3], [4]. In a half bridge power module, the mid-point experiences high dv/dt during switching transients.…”

Section: Introductionmentioning

confidence: 99%

Gate driver with high common mode rejection and self turn-on mitigation for a 10 kV SiC MOSFET enabled MV converter

Dalal

Christensen

Jorgensen

et al. 2017

2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe)

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This paper investigates gate driver design challenges encountered due to the fast switching transients in medium voltage half bridge silicon carbide MOSFET power modules. The paper presents, design of a reduced isolation capacitance regulated DC-DC power supply and a gate driver with an active Miller clamp circuit for a 10 kV half bridge SiC MOSFET power module. Designed power supply and the gate driver circuit are verified in a double pulse test setup and a continuous switching operation using the 10 kV half bridge silicon carbide MOSFET power module. An in-depth experimental verification and detailed test results are presented to validate the gate driver functionality. The designed gate driver circuit shows satisfactory performance with increased common mode noise immunity and protection against the Miller current induced unwanted turn on.

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“…The voltage balancing across the series-connected devices is mainly caused by the tolerance in device parameters, package/layout parasitic components, and gate signal timing delays [7][8][9]. Careful selection of power semiconductor devices, which have parameters with low spread and synchronizing gate-drive signals, are helpful in reducing voltages unbalance across the power devices.…”

Section: Introductionmentioning

confidence: 99%

“…Careful selection of power semiconductor devices, which have parameters with low spread and synchronizing gate-drive signals, are helpful in reducing voltages unbalance across the power devices. In addition to this, snubber circuits, active gate drive circuits, voltage clamping techniques [7][8][9][10][11], and new concepts of packaging as described in [12,13] have also been reported as interesting contributions in an attempt to reduce or even remove the voltage unbalance among the series-connected power devices.…”

Section: Introductionmentioning

confidence: 99%

Analysis of the Multi-Steps Package (MSP) for Series-Connected SiC-MOSFETs

et al. 2020

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In this paper, a multi-step packaging (MSP) concept for series-connected SiC-MOSFETs is analyzed. The parasitic capacitance generated by the dielectric isolation of each device in the stack has a significant impact on the dynamic behavior of SiC devices, which impacts the voltage-sharing performances. The study performed in this work reveals that the parasitic capacitance network introduced by the classical planar packaging unbalances the voltage across the series-connected SiC-MOSFETs. Therefore, a new drain-source parasitic capacitance network configuration provided by the MSP is proposed in order to improve the voltage balancing across the series-connected devices. The concept is introduced and analyzed thanks to equivalent models and time domain simulations. To verify the analysis, the voltage sharing between four series-connected 1.2 kV SiC MOSFETs is tested in a double pulse test setup. The experimental results confirm that the MSP has a better performance than the classical one in terms of voltage sharing. Furthermore, the proposed investigation shows that the MSP increases the middle point dv/dt of the switching cell. Sensitive analysis and thermal management considerations are also discussed in order to clarify the MSP limitations and indicate the ways to optimize the MSP from a thermal point of view.

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Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM

Abstract: Support has been received from the IEPE and APETT projects funded by Innovation Fund Denmark and the MV platform project funded by the Obel Family Foundation.

Cited by 41 publications

References 14 publications

A Fast-Switching Integrated Full-Bridge Power Module Based on GaN eHEMT Devices

A Fast-Switching Integrated Full-Bridge Power Module Based on GaN eHEMT Devices

Gate driver with high common mode rejection and self turn-on mitigation for a 10 kV SiC MOSFET enabled MV converter

Analysis of the Multi-Steps Package (MSP) for Series-Connected SiC-MOSFETs

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