Common mode current mitigation for medium voltage half bridge SiC modules

Abstract

Medium voltage 10 kV Silicon Carbide MOSFETs, introduce challenges regarding converter design. Very high rate of voltage change and capacitive couplings to for example cooling systems cause increased electromagnetic interference. The aim of this paper is to accurately model the capacitive coupling to a heat sink and experimentally validate the model. An analytic model of the heat sink is developed which is demonstrated to be in excellent agreement with experimental results. The experimental result validates the modelled heat sink network allowing engineers to choose a suitable grounding impedance to comply with the electromagnetic compatibility regulations. Common mode current mitigation for Medium Voltage Half Bridge SiC Modules CHRISTENSEN Nicklas EPE'17 ECCE Europe ISBN: 9789075815276 et CFP17850-ART P.1

Gate driver with high common mode rejection and self turn-on mitigation for a 10 kV SiC MOSFET enabled MV converter

“…The parasitic capacitance C σ(OUT) is a source of EMI that introduces CM current during the high dv/dt switching transitions [15], [16]. For improved EMI performance and owing to safety concerns, the heatsink on which the power module is mounted is grounded using a 278 Ω power resistor based on the analysis described in [3].…”

“…5 are different due to the internal gate resistance of the device and parasitic inductance in the gate-source loop. An analytical approach considering the SiC MOSFET parasitics as described in [3], [13], [14], was used to study the fluctuation of gate voltage due to Miller current. Taking into account the above mentioned considerations, a reference voltage of 0 V is chosen to avoid an occurrence, where the clamp is turned on before the voltage across the gate-source capacitance C gs reaches below the 2.6 V threshold voltage.…”

“…With latest technological improvements these devices are reaching the level of maturity to be considered for medium voltage and high power conversion applications e.g., solid state transformer [2]. Considering high dv/dt switching transients, intrinsic device parasitics together with parasitic capacitance external to the device are crucial and require careful optimization to utilize SiC MOSFETs at their full potential [3], [4]. In a half bridge power module, the mid-point experiences high dv/dt during switching transients.…”

Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM

“…The LTSpice model based on capacitances evaluated in ANSYS Q3D is verified using a double pulse test at a DC-link voltage of 5 kV. An experimental test bench was designed to ensure robust operation during high voltage switching [12]. The SiC power modules are powered from custom designed gate driver supplies [13], due to high coupling capacitance in commercially available medium voltage DC-DC supplies [14].…”

Parasitic Capacitance in Copper-Foiled Medium-Voltage Filter Inductors

“…Yet, the high dv/dt problem becomes more significant during the switching transitions of SiC MOSFETs [4]. Under the high dv/dt conditions, the parasitic capacitances of passive and active power components, such as the common-mode capacitance of gate drivers [5], [6], the ground capacitance of heatsink [7], the parasitic capacitance in power modules [8], [9], and the parasitic capacitance in transformers [10][11][12] and inductors [13][14][15], can bring large common-/differential-mode current into the converter circuit [13], causing electromagnetic interferences [4] and accelerating the aging of power components [16].…”