Board-level physical test performance of CSP/BGA packages need in depth characterization of loading parameters and material behavioral properties. In recent years, many calibration methods were adopted by the researchers and industries to improvise solder joint performances of packages. Effective and uniform board response is one of the critical challenges in developing test board to qualify package components for solder joint reliability qualification. In this paper, an improvised board type alternative to standard Joint Electron Device Engineering Council (JEDEC) board is developed for uniform stress/strain response. An axis symmetrical board is chosen in comparison to the current JEDEC board. The effectiveness of the two boards are compared with each other under extreme banding under controlled drop test simulation. The uniform stress–stain distribution is recorded maintaining the no-ring phenomenon by selecting optimal shock pulse parameters. Selected impact/shock pulse is decided by identifying the maximum impact energy absorbed by the board during the drop event. Board surface strain and stress data are captured 1–2 mm away near the components are quantified for higher strain rate. The board local strain rate on the board surface is recorded at a selected time-step to quantify the dynamic stresses along the component side surface on the board. The simulation is performed by using ANSYS software using implicit method. Both linear SOLID45 and quadratic SOLID95 elements are used to compare and correlate the results. Close forms of results were correlated with the previous theoretical results.

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Validation of surface mounted electronic devices for drop test performance is considered as one of the most challenging tasks for researchers to search for key dynamic parameters either by experimentation or by numerical simulation. It has not only become challenging task to capture some of the important parameters that affect board flexural rigidity, stiffness, dynamic stresses and strains, but also avoid stress concentrations near undesired locations resulting in non-uniform strain distribution throughout the test board. There is a requirement to simulate exact drop condition that quantifies high impact energy on the board and also control drop to improve the board surface stress/strain distribution measured should be independent from standoff stress region. In this paper, an effort to find the importance of viscous and linear hysteric damping characteristics on uniform board response has been made. The influence of damped responses during no ring impact has been analyzed. Two different types of computational models are developed and an approximate FEA numerical solutions are obtained to compare current JEDEC test board and alternative hexagonal boards at reduced computational time and challenging experimental cost. The effect of board responses with two types of linear damping models are considered to study the effect. An approach towards finding key parameters that affect stress/strain distribution under both free as well as constrained model has been made, with including different pulse shapes parameters into effect. Maximum board strains are validated and compared using Global FEA model and maximum stresses on the components are evaluated using cut boundary interpolation method. Comparative to empirical results data, an effort to improve uniform stress strain distribution of package solder joints has been made and results are correlated.

For past several years, industries are carrying out board level drop tests to calibrate JEDEC board and improve on simulation in order to quantify the solder joint reliability performance of their products. It has not only become a difficult to simulate exact drop condition but also a challenging task to capture some of the important parameters such as board flexural rigidity, stiffness, resulting in non-uniform strain distribution throughout the test board. Previous simulations reveal unreliable stresses on all 15 components during predominate mode, which resulted in grouping of the components by location for performing reliability analysis. In addition, current experimental test procedures are not only expensive but also time consuming. In order to reduce cost and time, predictive analytical models were developed to understand drop behavior and also the key factors effecting solder joint failures. The drop impact simulation was performed using the different pulse time duration input function by analytical Method and evaluate response characteristics of the JEDEC board system. In this paper parametric study is done in order to bring more realistic drop condition and to quantify stress /strain distribution throughout the test board independent from standoff region by analyzing the system as simplified continuous beam system with sine impact pulse with the consideration of singular value (predominate mode) of the natural frequency. In addition, FEA simulation is also performed by developing JEDEC global/local model to simulate the realistic drop test condition. Direct acceleration method is adopted and no ring phenomenon is validated. By adjusting the input pulse period from 1.0 to 2.5 times the system period reveal further increase in the maximum peeling stress and board surface strain due no ring effect. In order to match the current test case, the magnitude of board input acceleration is reduced to the current drop conditions to understand and improve in the efficiency of the test and to capture more stress strain data in all the components. Close forms of theoretical and analytical results were correlated with the results of current JEDEC finite element global model.

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