The measured switched polarization properties of integrated Pb(Zr,Ti)O3 (PZT) capacitors arrays have been found to show a small dependence on individual capacitor size in the range from 0.17 and 100 μm2. These thin (90 nm) PZT capacitors have low voltage switching properties with polarization saturation of <1.8 V with switched polarization for the smallest capacitors (0.17 μm2) still larger than 25 μC/cm2. The capacitor stack consisted of TiAlN hardmask/Ir/IrOx/PZT/Ir/TiAlN on either SiO2 dielectric or W plugs. The capacitor was patterned using 248 nm lithography and etched using only one mask. For wafers without W plugs, the Ir bottom electrode was not etched. For wafers with W plugs, the entire capacitor stack was etched and electrical connection to the bottom electrode was through the W plugs. The capacitors were integrated using SiO2 dielectrics and one level of Al metallization. These data suggest that high-density, ferroelectric capacitor-based memories may be feasible.
Abstract-In this work, the effects of plasma-parameter variations on charging damage to polysilicon-gate MOS capacitor test structures exposed to O 2 electron-cyclotron-resonance (ECR) plasmas are investigated. Results will show that charging damage is generated when large potential differences exist across the gate-oxide layers of the MOS capacitor test structures and that these potential differences can only occur in the presence of plasma nonuniformities. These results demonstrate the critical need for plasma uniformity during processing, in particular as device dimensions shrink and gate-oxide thicknesses decrease. The plasma parameters were varied by adjusting the neutral gas pressure and by independently biasing a circular grid and a ring electrode located above the wafer. The damage induced in the test wafers during the plasma exposure was characterized with ramp-voltage breakdown measurements. Radial profiles of the floating potential measured with a Langmuir probe were found to vary nonuniformly when the grid electrode was positively biased due to preferential depletion of electrons relative to ions beneath the grid electrode. An equivalent-circuit model of the test wafer and the wafer-stage electrode predicts that the silicon substrate acquires a potential equal to the average of the wafer surface potential. Comparisons of the calculated profiles of the potential difference across the gate-oxide layers of the test structures and whole-wafer maps of the breakdown-voltage measurements show that the majority of the damage occurs where the oxide potential difference is largest and that the damage only occurs in the presence of plasma nonuniformities.
We have demonstrated that the scaling of IrO x (Pb(Zr, Ti)O3:PZT)/Ir capacitors can be extended into the submicron regime. The submicron IrO x /PZT/Ir capacitors were fabricated using a one-mask stack-etch process, integrated with an SiO2 interlayer dielectric, and contacted with Al metallization. The aggregate electrical properties of integrated PZT capacitor arrays are shown to be nearly independent of individual capacitor area in the range between 102 µm2 and 0.12 µm2. In particular, switched polarization values of more than 30 µC/cm2 were obtained for PZT capacitors with an individual capacitor area of 0.12 µm2. This result suggests that the lateral scaling can be achieved down to 0.1 µm2. Through the use of appropriate diffusion barriers, hydrogen-robust submicron PZT capacitors are obtained. No degradation in ferroelectric properties of submicron PZT capacitors was observed under the test conditions. These results suggest that PZT capacitors can be integrated into a standard complementary metal oxide semiconductor (CMOS) process flow with minimal degradation.
Charging induced damage of thin gate dielectric during polysilicon gate etching in a high density decoupled plasma source was investigated for 0.16 and 0.24 μm gates on 30 Å nitrided gate oxide. The undoped polysilicon gates were etched with a HBr/He/O2 based process recipe. The optimized process recipe resulted in vertical profiles (89°–90°) with microloading of <1°. No notching of the polysilicon or punch through of the thin gate oxide was observed. Gate leakage and breakdown voltage measurements after gate formation were made on metal-oxide-semiconductor capacitor structures with antenna ratios ranging from 100:1 to 1000:1. These measurements did not exhibit any damage to the thin gate dielectric. In addition, no significant change in the damage characteristics was observed over a wide process window around the optimized recipe, i.e., increased over etch (OE) time, increased source power, or reduced bias power in the OE step. A soft landing scheme was used for the etching of poly gates. This scheme provides vertical profiles without punch through and with minimum damage to the thin gate oxide and the substrate.
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