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An advanced tunnel oxide layer process for 65 nm NOR-type floating-gate flash memory is proposed to improve tunnel oxide quality by an additive sacrificial oxide layer growth. The sacrificial oxide layer process effectively controls the thickness variation of tunnel oxide and improves the flatness of the SiO 2 /Si interface across the active area. The interface traps' generation during program/erase cycling of flash cells is found to be reduced, and the reliability property is significantly improved as compared to flash cells without the sacrificial oxide layer process. The technology is applicable to further scaled floating-gate flash memories.

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