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The interfacial atomic structures of 3C-SiC/Si(0 0 1) and the dislocation core structures related to generation and annihilation of stacking faults are clarified by aberration-corrected transmission electron microscopy combined with image processing called the ‘image subtraction and improved deconvolution (ISD)’ method. Details of the intrinsic interfacial structure are explained in terms of a two-dimensional network of partial edge dislocations and Lomer dislocations. Around the junction of the interface and a {1 1 1} stacking fault, a seven-membered ring of Si and C atom columns and interfacial steps are observed. On the other hand, a six-membered ring is observed at the intersection of two {1 1 1} stacking faults. Based on the results, the formation mechanism of the intrinsic interfacial structure and stacking faults during the growth process is discussed.

The annealing behavior of a lanthanum oxide thin film deposited on a silicon (001) substrate by electron-beam evaporation has been studied by aberration-corrected transmission electron microscopy (TEM), scanning TEM (STEM), and electron energy loss spectroscopy (EELS). We have developed a procedure for the precise measurement of thickness and interfacial roughness by taking advantage of features of aberration correction combined with the statistics of fluctuating crystalline edge positions. The results of the measurements and quantitative elemental analyses by STEM-EELS have revealed atomic diffusion and reactions during deposition and postdeposition annealing (PDA) at 300 and 500 °C. The channel mobility could be limited by Coulomb scattering before PDA, and by remote roughness scattering and remote phonon scattering after PDA at 500 °C. When we consider the large leakage current caused by oxygen defects in the as-deposited sample and the large equivalent oxide thickness of the thick Si-rich layer in the 500 °C-PDA sample, the gate properties of the 300 °C-PDA sample should be better than those of other samples, as shown by electrical measurements.

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