No abstract

Etching of molybdenum was demonstrated in two steps. Mo was first oxidized in an ozone gas ambient to form molybdenum oxide. It is shown that comparable oxide thicknesses can be obtained in ozone and oxygen but at lower temperatures for the former. Initial oxide growth is fast but then considerably slows down due to its diffusion-limited character. The metal-oxide thickness can be controlled by temperature and defines the amount of metal etch per cycle (EPC). XPS analysis showed that the thermally grown oxide is MoO3. In the second, wet-chemical step, MoO3 was dissolved selectively toward the Mo metal using an aqueous solution. The dissolution rate of amorphous MoO3 formed in O3 at temperatures below ∼230 °C is fast, but the dissolution of MoO3 formed at Tox > 230 °C was shown to be incomplete. Cross-section TEM showed a matrix of amorphous oxide with crystallized MoO3 islands, the latter more difficult to dissolve. However, the crystalline phase could be completely and selectively removed using a more concentrated NH4OH solution at an elevated temperature (70 °C). The EPC was determined for temperatures between 150 and 290 °C. The etch rates increased with temperature from 1–2 nm/cycle at 150 °C to 5–6 nm/cycle at 290 °C. This hybrid thermal-wet etching sequence is well suited for vertical and lateral recess etching as it shows a controlled and isotropic dissolution of polycrystalline Mo at the nanoscale. Furthermore, the process shows a progressive surface smoothening upon increasing the number of etching cycles.

The Gate-All-Around (GAA) Field-Effect-Transistor (FET) is proposed as a promising candidate to replace Fin FET. In GAA architecture, Si Nanowires (NWs), which are fabricated by selective etching of SiGe from Si/SiGe multilayer fin structure, are used as channel. One of the concerns for fabricating GAA architecture is residual Ge, which is diffused SiGe from the Si/SiGe multilayer stack, in the Si NWs after their release. This Ge residue is a concern, since it could cause a degradation in device performance. The roughness of the Si NWs’ surface, which is a further factor in the degradation of device performance, was also examined. In this study, residual Ge removal and surface roughness with commodity chemistry was investigated. Finally, it was confirmed that residual Ge could be completely removed from Si without increasing Si surface roughness by dH2O2.

As semiconductor devices continue to scale, it is important to evaluate new metals for narrower trench or via structures. Mo is a candidate because of its lower resistivity compared to the conventional metals, Cu or W. Mo is etched with wet chemistry using an oxidizer but increase in surface roughness is a problem. The model for increase in roughness is water insoluble MoO2 partially remains whereas MoO3 dissolves in the water via simultaneous "oxidation-dissolution" reactions. We have developed a novel cyclic process with O3 gas bake followed by oxidizer free wet process to separate the oxidation and dissolution and verified that surface roughness does not increase. The new process was tested with patterned wafer to look at residue on sidewall, pattern loading and oxygen diffusion. This method is showing promising results and is expected to be applied for use in manufacturing of future semiconductor devices.

Thermally activated ozone gas (TAO) was demonstrated as an alternative technology to conventional spin-on carbon (SOC) stripping. The SOC stripping rate with ozone gas was found to be a function of substrate temperature and actual ozone amount calculated from the ozone flow rate and concentration. Furthermore, work function metal (WFM) stripping rate showed a high selectivity to SOC films, and the amount of oxidation TiN, which is a WFM metal, was also equivalent to conventional technology of SOC stripping. This TAO gas process can be used in clean tools, making it a promising integrated solution for SOC stripping followed by post clean.