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In this paper, a low power and high performance threedimensional (3-D) stacking multimedia platform called "3D-PAC" is proposed. This platform is a heterogeneous integration composed of a low power design logic layer (2D-PAC) and a reconfigurable memory tier via 3-D technology. After extensive 3-D architecture exploration with Electronic System Level (ESL) simulation, there is a 54% performance speedup compared with the former 2-D architecture for certain multimedia applications. This chip is fabricated in TSMC 90nm generic CMOS technology. The area of 2D-PAC is about 7880 x 7880 µm 2 and the SRAM layer is about 3880 x 3880 µm 2 . Both layers are combined with 1,886 TSVs.

Today's embedded systems mostly target on portable devices, which are expected not only to be small, lightweight, fully functional, and real-time, but also to provide extremely long battery lifetime. Therefore, energy-efficiency has become a new challenge. Due to this reason, the power consumption is more and more important for the system on chip (SoC) design. In this paper, we discuss the 65nm DSP subsystem which provides a power optimized DSP subsystem for dual-core software development and SoC prototyping. The most important component of 65nm DSP subsystem is the 65nm Media Platform IC. In the 65nm Media Platform IC, the dynamic voltage & frequency scaling (DVFS) and power gating mechanism have been applied to reduce power dissipations with a novel Unified Power Format (UPF) flow. The 65nm Media Platform IC is fabricated in the TSMC 65nm CMOS technology, of which the estimated power dissipations are 40.97mW for 240MHz @1.0V and 56.47mW for 342MHz @1.2V respectively.

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