Abstract

ANSI-C algorithm abstraction refinement for RTL circuits is investigated, with the goal of reducing the complexity of bounded model checking. This new method abstracts an ANSI-C algorithm from a verified RTL circuit, and then optimizes the algorithm for the ANSI-C bounded model checker CBMC. When a spurious counterexample is generated, this method refines the ANSI-C algorithm in more details. Equivalence checking between ANSI-C algorithms and RTL circuits, and that between the ANSI-C algorithms and their optimized versions are needed. Comparisons with other methods show that this new method is efficient.

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This paper presents an efficient strategy to solve the satisfiability (SAT) problem for RTL designs. Boolean DPLL algorithm is extended into a unified procedure to solve the hybrid constraints combining the Boolean logic and arithmetic operations, and an efficient modeling method of RTL circuits is adopted. Powerful constraint propagation in both domains and efficient learning on the interface and arithmetic part are applied. The main contributions of this paper are the integration of constraint propagations in both domains and the propagating methods in word-level part using arithmetic operations. The experimental results demonstrate the efficiency of our approach.