This paper reports on the defect detection algorithm for the LSI wafer multilayer patterns, together with the result of evaluation. The multilayer patterns are constructed by the exposure after alignment between the wafer pattern and the reticle pattern for each chip. Consequently, the position relation between layers is different even for adjacent chips (interlayer registration error). The developed algorithm compares the gray‐level images of adjacent chips on the wafer and extracts the defect without being affected by the inter‐layer registration error. First, the pattern edge is extracted from the gray‐level image, and the position alignment is executed using the edges. Then, by eliminating the region where gray levels are equal, the regions are extracted for which the position alignment is unsatisfactory. The position alignment is attempted again for that region. This procedure is iterated. When the unmatched region of the pattern edge is sufficiently small, it is decided that the interlayer registration error is absorbed, and the unmatched region is extracted as the defect. An automatic visual inspection system was constructed and evaluated experimentally. As a result, it was verified that the whole chip area can be inspected, and the defect of 0.5 μm or more can be detected in a stable way.

This paper reports on an image processing algorithm and hardware for fast, precise inspection of LSI wafer patterns. In order to detect deep sub-micron defects such as 0.2 pm at high speed by grayscale image comparison, we must overcome the sampling errors that inevitably occur between two images during detection. For this purpose, we have developed a subpixel image alignment algorithm that infers the correct sampling position and creates the two resampled images with subpixel accuracy. We have also developed an 8-channel pipelined processor with gate arrays. It has 8 x 19,000 gates and can operate at 8 x 15 MHz. Evaluation of the system conjirmed that the accuracy of the subpixel image alignment was 0.16 pixels or less and that the inspection system could detect 0.1 8 pm defects at a pixel size of 0.25 pm for half-micron LSI wafer patterns with an inspection speed of 2.5 slcm2.

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SUMMARY An anomaly detection method based on multidimensional time‐series sensor data and using normal state models has been developed. The local subspace classifier (LSC) method is employed to handle the various normal states and the fast LSC method is proposed to reduce the computation time. Clustering is utilized to reduce the amount of data when searching in the fast LSC (FLSC) method. The effectiveness of the FLSC method is confirmed against data from real equipment. The FLSC method is 1 to 10 times as fast as the LSC method.

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