This article presents a correlation between dynamic power supply current and pattern sensitive faults in SRAMs. It is shown that the dynamic power supply current provides a window for observing the internal switching behavior of the memory cells. Switching of the logic state of a memory cell results in a transient current pulse in the power supply rails. A new current-testable SRAM structure is presented which can be used to isolate normal current transients from those resulting from pattern sensitivity. The new structure differs from traditional SRAM structures only in the way that power is distributed to the cells. The new structure allows for very high coverages of disturb-type pattern sensitivity using a simple algorithm of length 5n where n is the number of cells.

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