This article presents a correlation between dynamic power supply current and pattern sensitive faults in SRAMs. It is shown that the dynamic power supply current provides a window for observing the internal switching behavior of the memory cells. Switching of the logic state of a memory cell results in a transient current pulse in the power supply rails. A new current-testable SRAM structure is presented which can be used to isolate normal current transients from those resulting from pattern sensitivity. The new structure differs from traditional SRAM structures only in the way that power is distributed to the cells. The new structure allows for very high coverages of disturb-type pattern sensitivity using a simple algorithm of length 5n where n is the number of cells.

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We propose in this paper a testing method for CMOS circuits that is insensitive to process variations and leakage levels. This method is based on the tramient supply current ( i~~~) and on the observation that current levels f o r different circuits on a chip scale with different runs of the process. In this method, we introduce a very simple test circuit on-chip. Then, we apply a normalization procedure that allows us to use a single thresholdfor all chips in dif ferent processes without prior knowledge of the process to which the circuit under test belongs. Resultsfrom various circuits show that the method is capable of improving the detection capability of threshold-based iDDr testing forfaults that would othenvise go undetected due to leakage andprocess variation.