Testing of static random access memories by monitoring dynamic power supply current

Abstract

This article presents a correlation between dynamic power supply current and pattern sensitive faults in SRAMs. It is shown that the dynamic power supply current provides a window for observing the internal switching behavior of the memory cells. Switching of the logic state of a memory cell results in a transient current pulse in the power supply rails. A new current-testable SRAM structure is presented which can be used to isolate normal current transients from those resulting from pattern sensitivity. The new structure differs from traditional SRAM structures only in the way that power is distributed to the cells. The new structure allows for very high coverages of disturb-type pattern sensitivity using a simple algorithm of length 5n where n is the number of cells.

Technology and layout-related testing of static random-access memories

“…While IDDQ testing was fairly effective in detecting a general variety of CMOS defects not usually considered by functional testing, for example gate oxide short, punch-through and leakage, it was found to have some shortcomings [29]. It is mostly limited to fully complementary logic (one that ideally draws no current from the supply during quiescent steady state conditions, and draws current only during switching transients), and is typically slower than voltage-type testing.…”

“…As described a little later, there exists a relationship between the dynamic power supply current and a variety of SRAM defects causing pattern sensitive and stuck open faults. The technique described by Su and Makki [29] uses a novel technique for distributing power to the cell array, resulting in low area overhead and a high defect coverage of the above defects. Their built-in current monitors make the whole test scheme quite efficient.…”

“…Each class of defects resulted in a peculiar response of the dynamic power supply current IDv. The various fault models for the defects under consideration are illustrated in Figure 4 [29]. The various pattern sensitive defects modeled by the authors are enumerated below:…”

A novel wavelet transform based transient current analysis for fault detection and localization

“…Plusquellic et al [8] proposed the concept of Transient Signal Analysis (TSA) with distributed measurement points. Su et al [12] applied dynamic current monitoring techniques on SRAMS using extensive DFT strategy. De Paul et al [7] used the accumulated charge (computed by numerical integration of a current waveform) for signature comparison.…”

A bipartite, differential I/sub DDQ/ testable static RAM design

“…The idea of IDDQ testing is expanded for fault localization in [6]. In [8], a testable SRAM structure was proposed for observing the internal switching behavior of the memory cells. The proposed structure provides a very high coverage of disturb-type pattern sensitivity using a simple algorithm of complexity of 5n (n= number of memory cells).…”