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In the past, mechanical sawing of low-k devices always poise to be a big challenge to achieve good dicing quality. This is because of the weak mechanical properties of low-k dielectric material used. Moving forward, this challenge will be even greater with the introduction of ultra low-k dielectric material in 45nm and 32nm wafer node size. An alternative dicing process such as laser grooving is gaining popularity in resolving the low-k saw problems. This paper discusses the development works of laser grooving and the following saw process of CMOS 90nm and 45nm devices, both in flip chip and wire bond packages. The discussion also includes wafer surface contamination prevention, laser process parameters selection, Heat Affected Zone (HAZ) analysis and laser process defects. A series of package reliability stress was carried out to prove the robustness of the finalized process parameters and conditions.

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