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A technique to extract in-plane thermal conductivity of thin metallic films whose thickness is comparable to electron mean free path is described. Microscale constrictions were fabricated into gold films of thicknesses 43nm and 131nm. A sinusoidal voltage excitation across the constriction results in a local temperature rise. An existing technique known as scanning joule expansion microscopy, measures the corresponding periodic thermomechanical expansion with a 10nm resolution and determines the local temperature gradient near the constriction. A three-dimensional finite-element simulation of the frequency-domain heat transfer fits the in-plane thermal conductivity to the measured data, finding thermal conductivities of 82±7.7W∕mK for the 43nm film and 162±16.7W∕mK for the 131nm film, at a heating frequencies of 100kHz and 90kHz, respectively. These values are significantly smaller than the bulk thermal conductivity value of 318W∕mK for gold, showing the electron size effect due to the metal-dielectric interface and grain boundary scattering. The obtained values are close to the thermal conductivity values, which are derived from electrical conductivity measurements after using the Wiedemann–Franz law. Because the technique does not require suspended metal bridges, it captures true metal-dielectric interface scattering characteristics. The technique can be extended to other films that can carry current and result in Joule heating, such as doped single crystal or polycrystalline semiconductors.

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Over upcoming electronics technology nodes, shrinking feature sizes of on-chip interconnects and correspondingly higher current densities are expected to result in higher temperatures due to self-heating. This study describes a finite element based compact thermal modeling approach to investigate the effects of Joule heating on complex interconnect structures. In this method, interconnect cross section is assumed to be isothermal and conduction along the interconnect is retained. A composite finite element containing both metal and dielectric regions is used to discretize the interconnect stack. The compact approach predicts the maximum temperature rise in the metal to within 5–10% of the detailed numerical computations, while requiring only a fraction of elements. Computational time for the compact model solution is several seconds, versus many hours for the detailed solutions obtained through successive mesh refinement until grid independence is achieved. For a comparable number of elements, the compact model is in general much more accurate than the traditional finite element approach. To validate the simulations, temperature rise in a 500-link two-layer interconnect with a via layer was measured at several current densities. The compact method predicts the temperature rise of the 500-link chain to within 5% of the measurements thereby validating the method. The approach described here could be an efficient technique for full chip Joule heating simulations and for clock signal propagation simulations, which are performed as part of designing next generation chip architectures.

Effective cooling of electronic chips is crucial for reliability and performance of electronic devices. Steadily increasing power dissipation in both devices and interconnects motivate the investigation of chip-centric thermal management as opposed to traditional package-centric solutions. In this work, we explore the fundamental limits for heat removal from a model chip for various configurations. Temperature rise when the chip is embedded in an infinite solid is computed for different thermal conductivities of the medium to pin down the best that can be achieved with conduction based thermal management. Next, a chip attached to a spreader plate with convection boundary condition on top was considered. A brief review of interface thermal resistances and partitioning of overall thermal resistance is presented for current generation microprocessors. Based upon the analysis it is concluded that far-term cooling solutions might necessitate integration with chip/interconnect-stack to meet the challenges. In addition, this would require concurrent thermal and electrical design/fabrication of future high-performance microprocessors.