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This research is to design an effective buffer structure and its management for flash memory based high performance SSDs (Solid State Disks). Specifically conventional SSDs tend to show asymmetrical performance in read and /write operations, in addition to a limited number of erase operations. To minimize the number of erase operations and write latency, the degree of interleaving levels over multiple flash memory chips should be maximized. Thus, to increase the interleaving effect, an effective buffer structure is proposed for the SSD with a hybrid address mapping scheme and super-block management. The proposed buffer operation is designed to provide performance improvement and enhanced flash memory life cycle. Also its management is based on a new selection scheme to determine random and sequential accesses, depending on execution characteristics, and a method to enhance the size of sequential access unit by aggressive merging. Experiments show that a newly developed mapping table under the MBA is more efficient than the basic simple management in terms of maintenance and performance. The overall performance is increased by around 35% in comparison with the basic simple management.

Currently, SLC-MLC hybrid SSD (solid state disk) products become mature. Phase-change random access memory (PRAM) is one of the new non-volatile memory materials used to enhance the limitation of original SLC-MLC hybrid SSD. Through reorganizing the basic functional modes among SLC, MLC, and PRAM, we proposed a new hybrid SSD architecture named PRAM-SLC-MLC Hybrid SSD (PH-SSD), in which a hierarchical updating method is designed. The PH-SSD employs PRAM as a primary updating area, uses SLC as a secondary updating area, uses MLC for main data storage, and performs data migration via a small capacity DRAM. Based on this proper arrangement, the PH-SSD can improve write performance and lifetime of SSD significantly. Through simulation, the PH-SSD achieves over 240% speedup and prolongs the lifetime by up to 2-3 times compared with the previous architecture.