No abstract

This paper presents an experimental technique to characterize the damage evolution of the topside interconnections of power semi-conductor devices during power cycling tests. DC power cycling tests are done on Semikron SKIM 63 power modules, a solder-free module with silver sintered chips, ensuring the degradations to appear in the top layers only. The cycled substrates are then extracted from the test bench at different steps of the aging for analysis. Four-probe measurements are implemented on the chips so that the evolution of physical parameters representative of the degradation in the metallization and the bond wire contacts can be obtained. Finally, optical microscopy analysis of cross-sections at the wire bond contact interface is carried out to corroborate the electrical measurements to the crack length growth after specific aging intervals.

Experimental investigations on the effects of load sequence on degradations of bond-wire contacts of Insulated Gate Bipolar Transistors power modules are reported in this paper. Both the junction temperature swing ($$\Delta T_{j}$$ Δ T j ) and the heating duration ($$t_{ON}$$ t ON ) are investigated. First, power cycling tests with single conditions (in $$\Delta T_{j}$$ Δ T j and $$t_{ON}$$ t ON ), are performed in order to serve as test references. Then, combined power cycling tests with two-level stress conditions have been done sequentially. These tests are carried-out in the two sequences: low stress/high stress (LH) and high stress/low stress (HL) for both $$\Delta T_{j}$$ Δ T j and $$t_{ON}$$ t ON . The tests conducted show that a sequencing in $$\Delta T_{j}$$ Δ T j regardless of the direction “high-low” or “low–high” leads to an acceleration of degradations and so, to shorter lifetimes. This is more pronounced when the difference between the stress levels is large. With regard to the heating duration ($$t_{ON}$$ t ON ), the effect seems insignificant. However, it is necessary to confirm the effect of this last parameter by additional tests.