A novel method is proposed in order to calculate the probability of an SET resulting into SEU. The method is proposed to calculate the propagation of SET to the output gate at any time instant within the latching window. The method uses symbolic simulation and disjoint covers of appropriately formulated functions to take into consideration re-convergent paths and therefore more accurate calculations. This is evaluated experimentally on the benchmark circuits.

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Transient faults have become increasingly observable in combinational logic. This is due to the weakening of some inherent protective mechanisms that logic traditionally holds against such flawed spurious events. One of the aforementioned mechanisms relates to the propagation of transient faults along sensitizable paths. Existing literature that relies on logic simulation underestimates the number of sensitizable paths per circuit. This leads to inconclusive and overly optimistic results when a worst-case analysis is required. In this paper, we present a zero-suppressed binary decision diagram (ZBDD) centered framework, for a complete consideration of all potentially sensitizable paths per circuit. The proposed method is validated in logic paths by evaluating worst-case transient-wave electrical characteristics, such as maximum duration and corresponding amplitude at the circuit outputs.

In the current deep sub-micron technology, a small inaccuracy in computing the probability of occurrence of a soft error result in an unacceptably large chip failure rate. We propose a method that considers gate delays to determine accurately the probability of SET propagation resulting into an error. Disjoint covers of appropriately formulated functions are used for the probability computations in order to consider reconvergent paths in the circuit. The probabilities are calculated at the output gate at all time instants that SET can propagate within a latching window. Bayes' theorem is used to model the SET injection.978-1-4244-6455-5/10/$26.00 ©2010 IEEE

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