No abstract

Increasing power delivery and performance requirements for next-generation Intel microprocessors has led to the need for a high-capacitance low-inductance decoupling option very close to the die. An embedded array capacitor (EAC) is a large array capacitor embedded in the high-density interconnect (HDI) substrate core and provides a low-inductance path to the die. This paper describes technology development challenges encountered while enabling EACs on Intel's advanced microprocessors. Various package interfaces resulting from the EAC embedding showed very high stress and propensity to delaminate. These defects were addressed by tailoring suitable materials and process modifications during the manufacturing process. Expansion of the embedding material in the HDI substrate resulted in high C4 area warpage. This led to issues such as solder bump bridging, underfill voids, and reliability fails. The technology development challenges and the solution paths described in this paper are very useful to industry in understanding the integration of advanced decoupling options in ultrahigh-performance microprocessor packages.