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A previous model derivation of the maximum clock frequency (FMAX) distribution for a VLSI design is reviewed to enable pre-silicon predictions of frequency bins and process/design optimization for specific product targets. Model projections were compared with measured FMAX data for a 0 2 5 p microprocessor. In this paper, an additional comparison is performed with a 0 . 1 3~ microprocessor, illustrating the close agreement between the simulated and measured distributions in mean, variance, and shape for different values of temperature and supply voltage. The previous model revealed that within-die variations primarily reduce the mean FMAX, or reciprocally, increase the mean of the maximum critical path delay (T,,,,) distribution. In this paper, a closed-form analytical equation of the Tq,-mean increase is derived as an extension to the FMAX distribution model, which further elucidates the dependency on within-die variations. For a given set of process-and circuit-level parameters, this model provides insight into the delay guard-band required to achieve specific performance goals. Moreover, the model identifies the point of diminishing returns for redesigning critical paths in the tail of the timing histogram. To explore the region of validity, a model assumption for the shape of the critical path delay distribution is examined to guide practical VLSI design decisions.

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The ongoing decommissioning of conventional power plants decreases the installed reactive power reserves for voltage control in transmission grids. Hence, an efficient planning of compensation devices substituting this lack of reactive power is required. Grid operators must allocate these devices for steady-state voltage control and for dynamic voltage control ensuring voltage stability. A separate determination of this static and dynamic VAR demand, however, fails to exploit synergies and disregards that VAR compensation in steadystate reduces the reserves for dynamic compensation. This paper proposes a coupled determination of the system static and dynamic VAR demand. An optimisation method applying mixed-integer programming identifies an efficient allocation and portfolio consisting of different compensation technologies. It includes constraints for voltage limits during steady-state and contingencies as well as for long-term voltage stability. Results emphasise that the method identifies an efficient portfolio for various operation and fault scenarios, while providing the required voltage stability margin.