Maximum clock frequency distribution model with practical VLSI design considerations

Bowman, Keith; Samaan, Stefanie; Hakim, Nagib

doi:10.1109/icicdt.2004.1309942

Cited by 11 publications

(8 citation statements)

References 13 publications

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“…The value of d median that makes the equality hold is the median max delay for the collection of both hard and easy paths. In our case, the median of this distribution closely approximates the mean [5]. For a fixed resulting median max delay (d median ), this equation represents an implicit function connecting d nom,hard and dnom,easy.…”

Section: B Maximum Delay Distribution For Two Path Typesmentioning

confidence: 92%

“…The delay distributions are plotted in Figure 9. Notice the delay distributions are essentially identical and validate the max delay model (5) and the model delay assumption in Section II-C. The power distributions are plotted in Figure 10.…”

Section: Monte-carlo Validationmentioning

confidence: 94%

“…To further simplify SDGG, the desired guardband can be estimated using general critical path delay statistics. For example, the mean (µ) t cycle degradation from WID variations can be calculated using a t cycle distribution model that is based on general critical path delay statistics [4], [5], and used as the guardband. Alternately, general critical path delay impacts due to WID variations can be derived statistically and included appropriately in the WC skew corner for timing analysis, along with D2D variations [10].…”

Section: Ssta and Design Optimizationmentioning

confidence: 99%

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Comparative analysis of conventional and statistical design techniques

Burns

Ketkar

Menezes

et al. 2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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We explore the power benefits of changing a microprocessor path histogram through circuit sizing based on statistical timing analysis and optimization (STAO) versus a deterministic timing approach that uses statistical design to establish a global guardband followed by conventional optimization (SDGG). Using an analytical modeling approach, we quantify the differences in total power between the two approaches while maintaining an equivalent performance distribution. For a relative 1σ random WID stage delay variation of 5% and representative microprocessor critical paths, the analysis indicates that the STAO approach enables ∼2% power reduction over the SDGG approach. To achieve a 4% and 6% power reduction through the STAO approach, the process variation needs to increase by a factor of 2x and 4x, respectively.

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Section: B Maximum Delay Distribution For Two Path Typesmentioning

confidence: 92%

Section: Monte-carlo Validationmentioning

confidence: 94%

Section: Ssta and Design Optimizationmentioning

confidence: 99%

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Comparative analysis of conventional and statistical design techniques

Burns

Ketkar

Menezes

et al. 2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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“…Borkar et al [2] noted that technology scaling beyond 90nm leads to larger device parameter variations, which are changing the microprocessor design problem from deterministic to probabilistic. Bowman et al [4][5] [6] used statistical analysis to study the effects of device parameter variations. A model for the maximum clock frequency of a microprocessor (FMAX) is derived and compared against wafer sort data.…”

Section: Related Workmentioning

confidence: 99%

Implications of Device Timing Variability on Full Chip Timing

Annavaram

Grochowski

Reed

2007

2007 IEEE 13th International Symposium on High Performance Computer Architecture

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As process technologies continue to scale, the magnitude of within-die device parameter variations is expected to increase and may lead to significant timing variability. This paper presents a quantitative evaluation of how low level device timing variations impact the timing at the functional block level. We evaluate two types of timing variations: random and systematic variations. The study introduces random and systematic timing variations to several functional blocks in Intel® Core™ Duo microprocessor design database and measures the resulting timing margins. The primary conclusion of this research is that as a result of combining two probability distributions (the distribution of the random variation and the distribution of path timing margins) functional block timing margins degrade non-linearly with increasing variability.

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“…The detailed distribution model is provided in [14], [13], [24]. Figure 6 shows the performance of the different frequency distribution scenarios under the same cache access latency distribution.…”

Section: Sensitivity Experimentsmentioning

confidence: 99%

Process variation aware thread mapping for Chip Multiprocessors

Narayanan

Kandemir

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that identically-designed processor cores on the chip have non-identical peak frequencies and power consumptions. To cope with such a design, each processor can be assumed to run at the frequency of the slowest processor, resulting in wasted computational capability. This paper considers an alternate approach and proposes an algorithm that intelligently maps (and remaps) computations onto available processors so that each processor runs at its peak frequency. In other words, by dynamically changing the thread-to-processor mapping at runtime, our approach allows each processor to maximize its performance, rather than simply using chip-wide lowest frequency amongst all cores and highest cache latency. Experimental evidence shows that, as compared to a process variation agnostic thread mapping strategy, our proposed scheme achieves as much as 29% improvement in overall execution latency, average improvement being 13% over the benchmarks tested. We also demonstrate in this paper that our savings are consistent across different processor counts, latency maps, and latency distributions.With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that identicallydesigned processor cores on the chip have non-identical peak frequencies and power consumptions. To cope with such a design, each processor can be assumed to run at the frequency of the slowest processor, resulting in wasted computational capability. This paper considers an alternate approach and proposes an algorithm that intelligently maps (and remaps) computations onto available processors so that each processor runs at its peak frequency. In other words, by dynamically changing the thread-to-processor mapping at runtime, our approach allows each processor to maximize its performance, rather than simply using chip-wide lowest frequency amongst all cores and highest cache latency. Experimental evidence shows that, as compared to a process variation agnostic thread mapping strategy, our proposed scheme achieves as much as 29% improvement in overall execution latency, average improvement being 13% over the benchmarks tested. We also demonstrate in this paper that our savings are consistent across different processor counts, latency maps, and latency distributions.

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Maximum clock frequency distribution model with practical VLSI design considerations

Cited by 11 publications

References 13 publications

Comparative analysis of conventional and statistical design techniques

Comparative analysis of conventional and statistical design techniques

Implications of Device Timing Variability on Full Chip Timing

Process variation aware thread mapping for Chip Multiprocessors

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